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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MC92501/D
MC92501
Advance Information ATM Cell Processor
The ATM Cell Processor (MC92501) is an Asynchronous Transfer Mode (ATM) layer device composed of dedicated high-performance ingress and egress cell processors combined with UTOPIA Level 2-compliant physical (PHY) and switch interface ports (see Block Diagram). The MC92501 is a second generation ATM cell processor in MotorolaOs 92500 series. This document provides information on the new features offered by the second generation ATM cell processor. This document, combined with MC92500/D, provides the complete specication for the ATM cell processor. New Features of the MC92501: Implements ATM Layer Functions for Broadband ISDN According to ATM Forum UNI 4.0 and TM 4.0 Specications, ITU Recommendations, and Bellcore Recommendations Provides ABR Relative Rate Marking and EFCI Marking According to TM 4.0 Selective Discard CLP = 1 (or CLP = 0+1) Flow on Selected Connections UTOPIA Level 2 PHY Interface and UTOPIA ATM Layer Interface Supports Both Partial Packet Discard (PPD) and Early Packet Discard (EPD) Change ABR RM Cell Priority Support for CLP Transparency Existing MC92500 Features: Full-Duplex Operation at Data Rates up to 155 Mbit/sec Performs Internal VPI and VCI Address Compression for up to 64K VCs CLP-Aware Peak, Average, and Burst-Length Policing with Programmable Tag/Drop Action Per Policer Supports up to 16 Physical Links Using Dedicated Ingress/Egress MultiPHY Control Signals Each Physical Link Can Be Congured as Either a UNI or NNI Port Supports Multicast, Multiport Address Translation Maintains Both Virtual Connection and Physical Link Counters on Both Ingress and Egress Cell Flows Provides a Flexible 32-Bit External Memory Port for Context Management Automated AIS, RDI, CC, and Loopback Functions with Performance Monitoring Block Test on All 64K Connections Programmable 32-Bit Microprocessor Interface Supporting Big-Endian or Little-Endian Bus Formats Bidirectional UPC or NPC Design with up to Four Leaky Buckets Per Connection Supports a Programmable Number of Additional Switch Overhead Parameters Allowing Adaptation to Any Switch Routing Header Format Provides Per-Link Cell Counters in Both Directions
GC SUFFIX GTBGA CASE 1208 ORDERING INFORMATION MC92501GC GTBGA
This document contains information on a new product. Specications and information herein are subject to change without notice.
REV 1.2 2/98
TN98020500
(c) Motorola, Inc. 1998 MOTOROLA
MC92501 1
REPRESENTATIVE BLOCK DIAGRAM
INGRESS PHY IF UTOPIA IF CRC Check (OAM) MultiPHY Support INTERNAL SCAN INGRESS CELL PROCESSOR VP and VC Address Translation NPC/UPC Cell Counting OAM Operations Add Switch Parameters Microprocessor Cell Insertion/Extraction INGRESS SWITCH IF CRC Generation Independent Clock MICROPROCESSOR IF Cell Insertion Cell Extraction Cong Registers Maintenance Access MICROPROCESSOR IF UTOPIA IF
EXTERNAL MEMORY IF
EXT MEMORY IF
FMC GENERATION
EGRESS CELL PROCESSOR Multicast Translation Cell Counting OAM Operations Address Translation Microprocessor Cell Insertion/Extraction EGRESS SWITCH IF Extract Overhead CRC Check Independent Clock UTOPIA IF
EGRESS PHY IF UTOPIA IF CRC Gen (OAM) MultiPHY Support
MC92501 2
MOTOROLA
TABLE OF CONTENTS SECTION 1.
1.1. 1.2. 2.1. 2.2. 2.3. 3.1. 3.1.1. 3.2. 3.3. 3.4. 3.5.
ATM NETWORK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ATM Network Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ATM Network Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 System Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 MC92501 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 First Generation Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SECTION 2.
SECTION 3.
PACKET-BASED UPC Discard Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 AAL5 Packet Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Cell-Based UPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Partial Packet Discard (PPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Early Packet Discard (EPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Limited Early Packet Discard (Limited EPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SECTION 4. SECTION 5.
5.1. 5.2. 5.3. 5.4. 5.4.1. 5.4.1.1. 5.4.1.2. 5.4.1.3. 5.4.1.4. 5.4.2. 5.4.2.1. 5.4.2.2. 5.4.2.3. 5.4.2.4. 5.4.3. 5.4.3.1. 5.4.4. 5.4.4.1. 5.4.5. 5.5. 5.5.1. 5.6. 6.1. 7.1. 7.2. 7.2.1. 7.2.2. 8.1. 8.1.1. 8.1.2. 8.1.3.
SELECTIVE DISCARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Available Bit Rate (ABR) Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Overview and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 RM Cell Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 RM Cell Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Cell Marking (CI, NI, PTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Sources for Ingress Flow Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Ingress Flow Status from Global Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Ingress Flow Status from CellOs Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Ingress Flow Status from Context Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Logic of Ingress Flow Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Sources for Egress Flow Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Egress Flow Status from Global Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Egress Flow Status from CellOs Overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Egress Flow Status from Context Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Logic of Egress Flow Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Ingress ABR Marking Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Logic of Ingress ABR Marking Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Egress ABR Marking Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Logic of Egress ABR Marking Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Cell Marking Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Ingress Switch ABR Priority Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 An Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Egress Reset EFCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SECTION 6. SECTION 7.
CLP TRANSPARENCY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 INDIRECT EXTERNAL MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SECTION 8.
IMPROVED HOST INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 An Additional MDTACK Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Programmable MREQ Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Update the Definition of MWSH and MWSL Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SECTION 9. SECTION 10. SECTION 11.
11.1. 11.2. 11.2.1. 11.2.2. 11.2.3.
EGRESS OVERHEAD MANIPULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 UTOPIA LEVEL 2 PHY INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
General Register List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Status Reporting Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Interrupt Register (IR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Interrupt Mask Register (IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ATMC CFB Revision Register (ARR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MOTOROLA
MC92501 3
TABLE OF CONTENTS (CONTINUED)
11.2.4. 11.3. 11.3.1. 11.3.2. 11.3.3. 11.3.4. 11.4. 11.4.1. 11.4.2. 11.4.3. 11.4.4. 11.4.5. 11.4.6. 11.4.7. 11.4.8. 11.4.9. 11.4.10. 11.4.11. 11.4.12. 11.4.13. 11.4.14. 11.4.15. 12.1. 12.1.1. 12.2. 12.2.1. 12.2.2. 12.2.3. MC92501 Revision Register (RR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ingress Processing Control Register (IPLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Egress Processing Control Register (EPLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indirect External Memory Access Address Register (IAAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indirect External Memory Access Data Register (IADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ingress Processing Configuration Register (IPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Egress Processing Configuration Register (EPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ATMC CFB Configuration Register (ACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Egress Switch Interface Configuration Register (ESWCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Egress Switch Overhead Information Register 0 (ESOIR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microprocessor Configuration Register (MPCONR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maintenance Configuration Register (MACONR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ingress PHY Configuration Register (IPHCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Egress PHY Configuration Register (EPHCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC92501 General Configuration Register (GCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Egress Switch Overhead Information Register 1 (ESOIR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RM Overlay Register (RMOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLP Transparency Overlay Register (CTOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Context Parameters Extension Table Pointer Register (CPETP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Egress Overhead Manipulation Register (EGOMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Context Parameters Extension Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Common Parameters Extension Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CONTEXT PARAMETERS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Egress Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ingress Parameters: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Common Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 25 25 25 26 26 27 27 28 29 29 30 30 31 31 31 32 32 33 33 33 34 35 35 36 36 36 37
SECTION 12.
EXTERNAL MEMORY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
SECTION 13. SECTION 14.
14.1. 14.2. 14.3. 15.1. 15.2. 16.1. 16.2. 17.1. 17.2. 17.3.
DATA STRUCTURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
13.1. General Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 13.1.1. Reason . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Microproccessor Signals (MP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Ingress PHY Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Egress PHY Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
SECTION 15. SECTION 16. SECTION 17.
TEST OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Packaging Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Electrical Specification for Clocks and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Additional Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 256-Lead GTBGA Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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SECTION 1. ATM NETWORK 1.1. ATM Network Description
the transmitting end station through the switching systems to the receiving end station. An ATM switch contains a high-speed switching fabric that connects multiple line cards. The switching fabric connects the input port to the output port based on the switchOs routing table. The line card interfaces between the physical medium and the switching fabric by recovering incoming cells from the arriving bit stream or converting outgoing cells into a bit stream for transmission. An ATM swtich partitioned in this fashion can efciently handle multiple physical links by independently transferring each incoming ATM cell from its source port to its destination port, based on the switchOs routing table. ATM standards divide the tasks to be performed on each side of the switch fabric into PHY layer and ATM layer tasks. The PHY layer tasks are dependent on the physical medium that connects ATM switches. The ATM layer tasks operate at the cell level and are independent of the physical medium.
A typical ATM network consists of user end stations that transmit and receive 53-byte data cells on virtual connections (see Figure 1). Physical links and switching systems interconnect the virtual connections. A virtual connectionOs path is established at the beginning of the data transfer, maintained while the end-stations are communicating, and torn down after the transfer is complete. This transmission method increases the transfer speed because the determination of the path the data will take is done only at the beginning of the data transfer instead of when each data subblock or packet is transferred. On a given physical link, each connection is assigned a unique connection identier. The connection identier is placed in the header of each cell by the transmitting equipment and is used by the receiving equipment to route the cell to the next physical link on the connection path. All cells belonging to a specic virtual connection follow the identical path from
VCs
Switch
Switch VCs
Switch END STATIONS
Switch
Switch
Switch END STATIONS
SWITCH
LINE CARD SWITCHING FABRIC LINE CARD
CLK REC
PHY
MC92501 ATM LAYER FUNCTIONS
LINE CARD
Figure 1. MC92501 in an ATM Network Application
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1.2.
ATM Network Applications
The MC92501 performs the ATM layer functions in an ATM switch such as cell processing and routing. Since the MC92501 is an ATM layer device, it is PHY layer independent. Figure 2 illustrates a typical ATM line card. The MC92501 uses an external memory for storing the cells that it processes. In addition, the MC92501 offers an option to utilize an external address compression device accessed via the same external memory bus. The microprocessor is used for conguration, control, and status monitoring of the MC92501 and is responsible for initializing and maintaining the external memory. The MC92501 is the master of the external memory bus. At regular intervals, the MC92501 allows the microprocessor to access the external memory for updating and maintenance. System RAM can also be located on the line card. The MC92501 can support a DMA device to allow efcient data transfer to this RAM without processor intervention.
The physical interface (PHY-IF) implements the physical layer functions of the B-ISDN Protocol Reference Model. This includes the physical medium dependent functions required to transport ATM cells between the ATM user and the ATM switch (UNI) or between two ATM switches (NNI). The cells are transferred between the physical interface and the MC92501 using the UTOPIA Level 2 standard. The MC92501 implements B-ISDN UNI/NNI ATM layer functions required to transfer cells to and from the switch over virtual connections. These functions include usage enforcement, address translation, and Operation, Administration, and Maintenance (OAM) processing. The MC92501 provides context management for up to 65,536 (64K) Virtual Connections (VCs). The VCs can be either Virtual Path Connections (VPCs) or Virtual Channel Connections (VCCs). ATM cells belonging to a particular VCC on a logical link have the same unique Virtual Path Identier/Virtual Channel Identier (VPI/VCI) value in the cell header. Similarly, cells belonging to a particular VPC on the same logical link share a unique VPI.
RAM
MICROPROCESSOR
DMA DMA
EXTERNAL MEMORY
EXTERNAL ADDRESS COMPRESSION
MICROPROCESSOR BUS
EXTERNAL MEMORY BUS TO SWITCH
CLOCK RECOVERY
PHY-IF PHY-IF PHY IF
MC92501
FROM SWITCH
LINE CARD Figure 2. Typical MC92501 Line Card Application
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SECTION 2. FUNCTIONAL DESCRIPTION 2.1. System Functional Description
Provides 155 Mbit/sec throughput capacity and is physical layer independent. Optionally supports up to 16 physical links. Optionally congured as a User Network Interface (UNI) or Network Node Interface (NNI) on a per-link basis. Provides Available Bit RateRelative Rate (ABRRR) marking and EFCI marking according to TM 4.0. Supports advanced discard policies such as Selective Discard, Partial Packet Discard (PPD), Early Packet Discard (EPD), and Limited Early Packet Discard (Limited EPD). Operates in conjunction with an external memory (up to 16 MB) to provide context management for up to 64K virtual connections. Provides cell counter coherency on a per-connection basis by maintaining redundant copies of the counter tables and dynamically switching between them. Provides per-link cell counters in both directions. Provides per-connection Usage Parameter Control (UPC) or Network Parameter Control (NPC) using a leaky bucket design with up to four buckets per connection. Provides support for Operation, Administration, and Maintenance (OAM) Continuity Check function for all connections. Supports Virtual Path (VP) and Virtual Channel (VC) level alarm surveillance, OAM fault management loopback test, and OAM performance monitoring on all connections. Interfaces with either big-endian or little-endian microprocessors. Supports cell insertion into the cell streams using direct access registers which may be written by the microprocessor or by a DMA device. Supports copying cells from the cell streams using direct access registers which may be read by the microprocessor or by a DMA device. Supports multicast operation.
A serial transmission link operating at up to 155.52 Mbit/sec (PHY) is coupled to the MC92501 via a byte-based interface. The transmission link timing is adapted to the MC92501 and switch timing by means of internal cell buffers. A common clock supplies both the PHY IF and MC92501. The host microprocessor initializes and provides real-time control information to the data-ow chips (PHY IF and MC92501) using slave accesses. The MC92501 operates in conjunction with an external connection memory, which provides one context entry for each active connection. The entry consists of two types of context parameters: static and dynamic. The static parameters are loaded into the context memory when the VC is established, and are valid for the duration of that connection. The static parameters include trafc descriptors, OAM ags, and ATM switch parameters. The dynamic context parameters include cell counters, UPC/NPC elds, and OAM parameters. The dynamic parameters can be modied while a particular connection is being processed. The microprocessor can access the external memory through the MC92501 to collect trafc statistics and to update the OAM parameters. During normal cell processing, the MC92501 has exclusive access to the external memory and maintains external memory coherency. At user-programmable intervals, the MC92501 provides the microprocessor with a Omaintenance slot.O During this time, cell processing is halted and control of the external memory bus is relinquished. The break in cell processing is made possible by the difference between the MC92501 cellprocessing rate and the line rate. The microprocessor can use the maintenance slot for any of the following tasks: Connection setup and tear down Statistics collection Updating OAM parameters of active connection The microprocessor is responsible for the external memory coherency during the maintenance interval.
2.3.
First Generation Features
2.2.
MC92501 Functional Description
MC92501 General Features: Implements ATM layer functions for broadband ISDN according to CCITT recommendations, ATM Forum UNI 4.0 and TM 4.0 specications, and ITU and Bellcore recommendations.
The MC92501 is a second generation ATM cell processor that enhances the MC92500 (rst generation) functionality. The MC92501 is backwards-compatible and pincompatible with the MC92500. This document describes the second generation enhancements and is meant to supplement the MC92500 specication. The MC92500 specication can be ordered from the Motorola Literature Center by requesting document MC92500/D.
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SECTION 3. PACKET-BASED UPC DISCARD ALGORITHMS 3.1. Introduction
The UPC is a two-state machine: discarding and notdiscarding. See Figure 4. While the UPC is in the not-discarding state, it performs normal cell-based operation with tagging and policing counter updates. The UPC transitions from the not-discarding to the discarding state on the rst discarded cell. While the UPC is in the discarding state, it does not update the UPC bucket but it does increment the policing discard counter. When in the discarding state and the last cell of a packet is received, there are two options: N If all the cells belonging to that packet were discarded, then this last cell is discarded. N If not all the cells belonging to that packet were discarded, then this means that the packet was truncated and this last cell is admitted in order to delineate the corrupted packet from the next packet. There is however one exception: if this last cell is violating cell-based UPC then it is discarded. Figure 5 illustrates an example for the PPD algorithm. A UPC policy violation occurs during the transmission of the rst packet. The UPC detects the violation and discards the remainder of the packet except for the last cell. The last cell of the rst packet is transmitted to avoid the concatenation of the corrupted packet with the subsequent Packet #2. If the UPC detects that the rst cell of Packet #3 violates its policy then Packet #3 is truncated. Packet #3Os last cell is not transmitted because it cannot be admitted by the cell-based UPC. Packet #4 is not transmitted either because its rst cell violates the UPC policy.
The MC92501 UPC function performs cell-based discard or packet-based discard according to ATM Forum TM 4.0. It supports packet discard on VC connections AAL5 packets (not including OAM cells). The MC92501 also performs Partial Packet Discard or Early Packet Discard. The MC92501 offers four modes of UPC operation on a perconnection basis: Cell-Based UPC, Partial Packet Discard (PPD), Early Packet Discard (EPD), and Limited Early Packet Discard (Limited EPD). These modes are selected on a perconnection basis using the IUOMNIngress UPC Operation Mode bit in the Common Extension Parameters Table. Packetbased UPC is enabled globally by the IPCVNIngress Features Enable bit in the ACR register. 3.1.1. AAL5 Packet Definition
A packet is dened as a stream of user cells belonging to the same virtual connection that has a series of one or more cells with the PTI[0] bit set to 0 and the last PTI[0] bit set to 1. (See Figure 3.)
3.2.
Cell-Based UPC
This is the default mode. The MC92501 discards cells on a per-cell basis as dened in MC92500/D.
3.3.
Partial Packet Discard (PPD)
According to the PPD algorithm, if a cell is discarded then all subsequent cells belonging to that packet are discarded up to but not including the last cell. Following is a detailed explanation of the UPC function.
CELL STREAM
PTI[0] = 1
PTI[0] = 0
PTI[0] = 0
PTI[0] = 1
PTI[0] = 0
LAST CELL OF PACKET 0
PACKET 1
FIRST CELL OF PACKET 2
Figure 3. Delineation of a Packet Within a Cell Stream
NOT-DISCARDING LAST CELL OF PACKET ARRIVES If all cells within a packet are discard OR If the last cell is violating UPC policy then discard the last cell If not all calls within packet discarded, then admit last cell DISCARDING
CELL VIOLATES UPC POLICY
Figure 4. UPC Discarding State Machine
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Packet #1 Input Stream
Packet #2
Packet #3 Packet #4
UPC Discard Decision
Output Stream
L
Figure 5. Partial Packet Discard
3.4.
Early Packet Discard (EPD)
According to the EPD algorithm, the decision to discard a packet takes place only at the beginning of a packet. This means that the complete packet is either fully discarded or fully passed. The following explains how EPD is implemented. When the EPD is discarding cells, the buckets are not updated but the policing discard counter is incremented. When the EPD decides that a frame should be passed this means that: N All tagging buckets continue to work in a cell-based fashion. N All discarding buckets perform their calculations as if the limit parameter is innite, and therefore increment the bucket content and do not discard any cells. As a result, their bucket content can be greater than their bucket limit. N The MC92501 may increment its police tagging counter. Figure 6 illustrates an example for the EPD algorithm. A cell within the rst packet violates the UPC, but due to EPD this packet is fully passed. Since the rst cell of Packet #2 violates the UPC, the second packet is fully discarded. Likewise, cells within Packet #3 violate the UPC, but this packet is not discarded. Since the fourth packet comes after a relatively
long time, which allows the UPC buckets to drain, Packet #4Os cells do not violate the UPC policy.
3.5.
Limited Early Packet Discard (Limited EPD)
One disadvantage of the EPD algorithm is that once it decides to admit a packet it cannot change its decision until the last cell of that packet. In the case of big packets, the switch can run into congestion. Using the Limited EPD algorithm, a connection can stop passing cells because of EPD once it reaches a predened limit. That limit, in the case of the MC92501, is reached once the rst bucket starts discarding cells. The rst bucket should have the same parameters as one of the other buckets except for the limit, which is bigger. Figure 7 describes a UPC which contains three buckets. The rst bucket is for limiting EPD, and there are two other buckets. The rst and second buckets share the same parameters except for the limit. Therefore, their bucket content is always the same, although the second bucketOs content is higher than its limit and cells are admitted by the EPD algorithm. When the rst bucket reaches its limit, then cells will be discarded. Figure 8 describes the EPD and Limited EPD functions.
Packet #1 Input Stream
Packet #2
Packet #3
Packet #4
UPC Discard Decision
Output Stream Figure 6. Early Packet Discard
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Limit
Limit Limit First Bucket Second Bucket
Figure 7. Limited Early Packet Discard
.
Third Bucket
Input Stream
Packet #1
Packet #2
Packet #3
Packet #4
First Bucket Limit
Other BucketsO Limit
EPDUPC Output Stream
Limited EPDUPC Output Stream Figure 8. Difference Between Early Packet Discard and Limited Early Packet Discard
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SECTION 4. SELECTIVE DISCARD
ATM Forum TM 4.0 denes procedures according to which cells can be discarded by network elements. A switching element may discard cells belonging to selected connections or cells whose CLP = 1 in case of congestion. This function is called selective discard and it is implemented by the MC92501. Selective discard is enabled by the ICNGNGlobal Ingress Congestion Notication bit in the Ingress Processing Control Register (IPLR). Selective discard can be enabled on a per-connection basis by the ISDMNIngress Selective Discard Operation Mode eld in the Common Parameters Extension Word. This eld determines whether selective discard is enabled and whether selective discard is performed on CLP = 1 or on CLP = 0+1 trafc. Selective discard can be enabled globally by the IPCVNIngress Enable bit in the ATMC CFB Conguration Register (ACR).
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SECTION 5. AVAILABLE BIT RATE (ABR) SUPPORT 5.1. Overview and Features
Checks CRC on received RM cells and generates CRC for transmitted RM cells. Provides different priority to RM cells. Can copy RM cells to the microprocessor or remove them from the ow.
The MC92501 provides a full Available Bit Rate (ABR) solution for switch behavior relative rate marking and EFCI marking in accordance with ATM Forum TM 4.0. It also provides the switch fabric with an interface to increase the RM cellsO trafc priority. Following is a list of features: Performs Relative Rate (RR) marking on Forward Resource Management (FRM) and/or Backward Resource Managment (BRM) cells, on selected connections. This feature is enabled by either setting the ATMC CFB Conguration RegisterOs (ACR) VP RM Cell PTI (NPRP) bit or by setting the PTI eld in the cellOs header to O110BO. Performs EFCI marking on non-RM cells whose PTI[2] = 0, on selected connections. This feature is enabled by either control registers or by elds that it gets from the overhead of cells which are received from the switch fabric. Resets EFCI on non-RM cells whose PTI[2] = 0, on selected connections.
5.2.
RM Cell Definition
A cell is an RM cell if and only if at least one of the following conditions is met: The cell belongs to a VC connection and its PTI = 6. The cell belongs to a VP connection, its VCI = 6, and its PTI = 6. The cell belongs to a VP connection, its VCI = 6, and the ATMC CFB Conguration Register has theVPRPNVP RM Cell PTI bit set.
5.3.
RM Cell Fields
Header = 5 bytes 8 GFC/ VPI VPI VCI PTI CLP HEC PID
Payload = 48 bytes
8
2x8 ER
2x8 CCR
2x8 MCR
4x8 QL
4x8 SN
30 x 8 + 6 Reserved
10 CRC-10
DIR
BN
CI
NI
RA
Reserved
1
1
1
1
1
3
NOTES: PID = 1 DIR = Direction 0 = Forward RM cell 1 = Backward RM cell BN = Backward Explicit Congestion 0 = Generated by source 1 = Generated not by the source CI = Congestion Indication NI = No Increase Bit ER = Explicit Rate CCR = Current Cell Rate MCR = Minimum Cell Rate CRC - 10
Figure 9. RM Cell Fields
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5.4.
Cell Marking (CI, NI, PTI)
Figure 10 illustrates two MC92501 devices connected to a switch fabric. In this example, the ABR ow travels from left to right. This means that data cells are owing from left to right, FRM cells are owing from left to right, and BRM cells are owing from right to left. The switch marks FRM and user cells
Ingress Flow Status
owing downstream, and BRM cells owing upstream. This switch function can be implemented in the ingress of MC92501 #1 and in the egress of MC92501 #2. MC92501 #1 marks cells because of the ingress ow status (for example, ingress ow congestion) while MC92501 #2 marks cells because of the egress ow status.
Egress Flow Status
Ingress User Cell Marking (EFCI) Ingress FRM Cell Marking (CI or NI) Egress BRM Cell Marking (CI or NI) Ingress BRM Cell Marking (CI or NI)
Egress User Cell Marking (EFCI) Egress FRM Cell Marking (CI or NI)
EFCI, FRM
Ingress Switch Fabric Egress MC92501 #1
Egress
BRM
Ingress MC92501 #2
Downstream Direction Upstream Direction
Figure 10. ABR Flow Cell Marking Example
The MC92501 can take the following actions in response to the ingress ow status: Perform EFCI marking on ingress cells; i.e., set PTI[1] bit in cells on which PTI[2] = 0. Set CI or NI in ingress FRM cells. Set CI or NI in egress BRM cells. The MC92501 can take the following actions in response to the egress ow status: Perform EFCI marking on egress cells; i.e., set PTI[1] bit in cells on which PTI[2] = 0. Set CI or NI in egress FRM cells. Set CI or NI in ingress BRM cells. Figure 11 is an overview of the MC92501 marking scheme.
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MC92501 13
Global Reg. Set CI CellOs Overhead Context Bit Ingress Status Collection Ingress Flow Status Ingress Action: Marking Set NI Set PTI
Global Registers Global Registers Context Bits Cell Type
Global Reg. CellOs Overhead Context Bit Egress Status Collection Egress Action: Marking
Set CI Set NI Set PTI
Egress Flow Status
Figure 11. Cell Marking Scheme
There are various ways to inform the MC92501 that it should mark a cell due to the ingress ow status or the egress ow status. This scheme also shows that the status of the ingress ow, the status of the egress ow, global registers, a context bit, and the cell type impact the decision of setting CI, NI, and PTI. Following is a detailed description of each of the function boxes. 5.4.1. Sources for Ingress Flow Status Section 5.4.1.2 for details on enabling of IFSNOverhead Ingress Flow Status bit and its location.) When the MC92501 receives that cell, it copies the bit into the CIFSNConnection Ingress Flow Status bit in the Common Parameters Extension Word of connection #n. The MC92501 can be programmed that in such a case it will mark ingress FRM cells or perform EFCI marking. 5.4.1.4. Logic of Ingress Flow Status The ingress ow status equals 1 if: IAME = 1 OR IFS = 1 and EIAS = 1 and egress = 1 OR CIFS = 1 and EIAS = 1 and ingress = 1 Where: IAME = Global Ingress ABR Mark Enable IFS = Overhead Ingress Flow Status EIAS = Global IFS Enable CIFS = Connection IFS Enable Egress = Programmed Overhead Egress Bit Ingress = Programmed Overhead Ingress Bit 5.4.2. Sources for Egress Flow Status
The ingress ow status is gathered from three sources: global register, cellOs overhead, or context bit. 5.4.1.1. Ingress Flow Status from Global Register The switch fabric can notify the MC92501 that it should mark cells because of the ingress ow status by setting the IAMEN Global Ingress ABR Mark Enable bit in the Ingress Processing Control Register (IPLR). 5.4.1.2. Ingress Flow Status from CellOs Overhead The switch fabric can notify the MC92501 that it should mark cells because of the ingress ow status of connection #n by setting the IFSNOverhead Ingress Flow Status bit in the overhead of egress cells belonging to that connection. The location of this bit in the overhead is programmable using the EIBYNIFS Byte Location bit and the EIBINIFS Bit Location bit in the Egress Switch Overhead Information Register 1 (ESOIR1). This bit is enabled by the EIASNGlobal IFS Enable bit in the Egress Switch Interface Conguration Register (ESWCR). The MC92501 can be programmed that in such a case it will mark egress BRM cells. 5.4.1.3. Ingress Flow Status from Context Memory The switch fabric can notify the MC92501 that it should mark cells because of the ingress ow status of connection #n by setting the IFSNOverhead Ingress Flow Status bit in the overhead of egress cells belonging to that connection. (See
The egress ow status is gathered from three sources: global register, cellOs overhead, and context memory. 5.4.2.1. Egress Flow Status from Global Register The switch fabric can notify the MC92501 that it should mark cells because of the egress ow status by setting the EAMEN Global Egress ABR Mark Enable bit in the Egress Processing Control Register (EPLR). 5.4.2.2. Egress Flow Status from CellOs Overhead The switch fabric can notify the MC92501 that it should mark cells because of the egress ow status of connection #n by setting the EFSNOverhead Egress Flow Status bit in the overhead of egress cells belonging to that connection. The
MC92501 14
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location of this bit in the overhead is programmable using the EEBYNEFS Byte Location bit and the EEBINEFS Bit Location bit in the Egress Switch Overhead Information Register 1 (ESOIR1). This bit is enabled by the EEASNGlobal EFS Enable bit in the Egress Switch Interface Conguration Register (ESWCR). The MC92501 can be programmed that in such a case it will mark egress FRM cells or perform EFCI marking. 5.4.2.3. Egress Flow Status from Context Memory The switch fabric can notify the MC92501 that it should mark cells because of the egress ow status of connection #n by setting the EFSNOverhead Egress Flow Status bit in the overhead of egress cells belonging to that connection. (See Section 5.4.2.2 for details on enabling of EFSNOverhead Egress Flow Status bit and its location.) When the MC92501 receives that cell, it copies the bit into the CEFSNConnection Egress Flow Status bit in the Common Parameters Extension Word of connection #n. The MC92501 can be programmed that in such a case it will mark ingress BRM cells. 5.4.2.4. Logic of Egress Flow Status The egress ow status equals 1 if: EAME = 1 OR EFS = 1 and EEAS = 1 and egress = 1 OR CEFS = 1 and EEAS = 1 and ingress = 1 Where: EAME = Global Egress ABR Mark Enable EFS = Overhead Egress Flow Status EEAS = Global EFS Enable CEFS = Connection EFS Enable Egress = Programmed Overhead Egress Bit Ingress = Programmed Overhead Ingress Bit 5.4.3. Ingress ABR Marking Bits
All cell marking on the ingress is enabled on a perconnection basis by the CIMENConnection Ingress Marking Enable bit in the Common Parameters Extension Word. 5.4.3.1. Logic of Ingress ABR Marking Bits The CI bit is set if: FRM cell and CIME = 1 and ingress ow status = 1 and ISFCE = 1 OR BRM cell and CIME = 1 and egress ow status = 1 and ISBCE = 1 The NI bit is set if: FRM cell and CIME = 1 and ingress ow status = 1 and ISFNE = 1 OR BRM cell and CIME = = 1 and egress ow status = 1 and ISBNE = 1 The PTI[1] bit is set if: PTI[2] = 0 and CIME = 1 and ingress ow status = 1 and ISPE = 1 Where: CIME = Connections Ingress Marking Enable FRM Cell = Cell marked as FRM cell BRM Cell = Cell marked as BRM cell Ingress Flow Status = Set as dened in Section 5.4.1.4 Egress Flow Status = Set as dened in Section 5.4.2.4 ISFCE = Global Ingress Set FRM CI Enable ISFNE = Global Ingress Set FRM NI Enable ISPE = Global Ingress Set PTI Enable ISBCE = Global Ingress Set BRM CI Enable ISBNE = Global Ingress Set BRM NI Enable 5.4.4. Egress ABR Marking Bits
The MC92501 can mark cells as a result of either ingress ow status or egress ow status. In the case where ingress ow status is asserted, the MC92501 can perform one or more of the following: Set CI bit in an ingress FRM cell N when the ISFCEN Global Ingress Set FRM CI Enable bit in the Ingress Processing Conguration Register (IPCR) is set. Set NI bit in an ingress FRM cell N when the ISFNEN Global Ingress Set FRM NI Enable bit in the IPCR is set. Set PTI[1] bit in an ingress cell whose PTI[2] = 0 N when the ISPENGlobal Ingress Set PTI Enable bit in the IPCR is set. In the case where egress ow status is asserted, the MC92501 can perform one or more the following: Set CI bit in an ingress BRM cell N when the ISBCEN Global Ingress Set BRM CI Enable bit in the IPCR is set. Set NI bit in an ingress BRM cell N when the ISBNEN Global Ingress Set BRM NI Enable bit in the IPCR is set.
The MC92501 can mark cells as a result of either ingress ow status or egress ow status. In the case where egress ow status is asserted, the MC92501 can perform one or more of the following: Set CI bit in an egress FRM cell N when the ESFCEN Global Egress Set FRM CI Enable bit in the Egress Processing Conguration Register (EPCR) is set. Set NI bit in an egress FRM cell N when the ESFNEN Global Egress Set FRM NI Enable bit in the EPCR is set. Set PTI[1] bit in an egress cell whose PTI[2] = 0 N when the ESPENGlobal Egress Set PTI Enable bit in the EPCR is set. In the case where ingress ow status is asserted, the MC92501 can perform one or more the following: Set CI bit in an egress BRM cell N when the ESBCEN Global Egress Set BRM CI Enable bit in the EPCR is set. Set NI bit in an egress BRM cell N when the ESBNEN Global Egress Set BRM NI Enable bit in the EPCR is set. All cell marking on the egress is enabled on a perconnection basis by the CEMENConnection Egress Marking Enable bit in the Common Parameters Extension Word.
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MC92501 15
5.4.4.1. Logic of Egress ABR Marking Bits The CI bit is set if: FRM cell and CEME = 1 and egress ow status = 1 and ESFCE = 1 OR BRM cell and CEME = 1 and ingress ow status = 1 and ESBCE = 1 The NI bit is set if: FRM cell and CEME = 1 and egress ow status = 1 and ESFNE = 1 OR BRM cell and CEME = 1 and ingress ow status = 1 and ESBNE = 1 The PTI[1] bit is set if: PTI[2] = 0 and CEME = 1 and egress ow status = 1 and ESPE = 1
Where: CEME = Connections Egress Marking Enable FRM Cell = Cell marked as FRM cell BRM Cell = Cell marked as BRM cell Ingress Flow Status = Set as dened in Section 5.4.1.4 Egress Flow Status = Set as dened in Section 5.4.2.4 ESFCE = Global Egress Set FRM CI Enable ESFNE = Global Egress Set FRM NI Enable ESPE = Global Egress Set PTI Enable ESBCE = Global Egress Set BRM CI Enable ESBNE = Global Egress Set BRM NI Enable 5.4.5. Cell Marking Examples
Figure 12, Figure 13, and Figure 14 provide examples for CI and NI marking.
Microprocessor NOTE 1 NOTE 3 NOTE 2
NOTE 4
Switch Fabric
MC92501 #1 Downstream Direction Upstream Direction
MC92501 #2
NOTES: 1. Initially the microprocessor congures the MC92501 #1 as follows: Sets the ISFCENGlobal Ingress Set FRM CI Enable bit. Sets the CIMENConnection Ingress Marking Enable bit for selected ABR connections. 2. The switch fabric informs the microprocessor that ingress ABR queues have reached some limit. 3. The microprocessor sets the IAMENGlobal Ingress ABR Mark Enable bit. 4. The MC92501 sets the CI bit for FRM cells belonging to the selected ABR connections.
Figure 12. Enable Marking CI Bits of Ingress FRM Cells
MC92501 16
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Microprocessor NOTE 1
Switch Fabric NOTE 3 NOTE 2
MC92501 #1 Downstream Direction Upstream Direction
MC92501 #2
NOTES: 1. Initially the microprocessor congures the MC92501 #1 as follows: Sets the EIASNGlobal IFS Enable bit. Sets the ESBNENGlobal Egress Set BRM NI Enable bit. Programs the location of the IFSNOverhead Ingress Flow Status bit by writing to the EIBYNIFS Byte Location and the EIBINIFS Bit Location elds. On connection setup the microprocessor congures the MC92501 #1 as follows: Sets the CEMENConnection Egress Marking Enable bit for selected ABR connections. 2. The switch detects that the ingress queue of connection #n has reached a limit. It sets ingress ow status bit on the overhead of cells belonging to that connection. 3. The MC92501 sets the NI bit of BRM cell belonging to connection #n.
Figure 13. Egress Flow Contains Ingress Flow Status and Causes the MC92501 to Mark BRM Cell NI Field
Microprocessor NOTE 1
NOTE 2 NOTE 3 Switch Fabric NOTE 4
MC92501 #1 Downstream Direction Upstream Direction
MC92501 #2
NOTES: 1. Initially the microprocessor congures the MC92501 #2 as follows: Sets the EEASNGlobal EFS Enable bit. Sets the ISBCENGlobal Ingress Set BRM CI Enable bit. Programs the location of the EFSNOverhead Egress Flow Status bit by writing to the EEBYNEFS Byte Location and the EEBIN EFS Bit Location elds. On connection setup the microprocessor congures the MC92501 #2 as follows: Sets the CEMENConnection Egress Marking Enable bit for selected ABR connections. 2. The switch detects that the egress queue of connection #n has reached a limit. It sets egress ow status bit on the overhead of cells belonging to that connection. 3. The MC92501 copies the overhead egress ow status bit into the CEFSNConnection Egress Flow Status bit and effectively sets it. 4. The MC92501 sets the CI bit of BRM cells belonging to connection #n.
Figure 14. Egress Flow Contains Egress Flow Status for Connection #n Causes the MC92501 to Mark CI Bit of All Ingress BRM Cells Belonging to That Connection
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5.5.
Ingress Switch ABR Priority Interface
The MC92501 denes an 8-bit eld which can be overlayed on bits of the ingress switch parameters belonging to RM cells. In applications where the overlayed switch parameter eld is a priority eld which is used by the switch fabric, RM cells can gain higher priority in passing the switch and thus enable shortening the feedback loop for ABR. The MC92501 performs this eld overlay if one of the following occurs: An ingress BRM cell is received and both the IBOEN Ingress BRM Overlay Enable bit and the IROENIngress RM Overlay Enable bit are set.
An ingress FRM cell is received and both the IFOEN Ingress FRM Overlay Enable bit and the the IROEN Ingress RM Overlay Enable bit are set. Once the MC92501 is enabled, it uses the ROLNRM Overlay Location eld in order to locate one byte out of 12 bytes on the ingress switch parameters. This byte is overlaid by the ROFNRM Overlay eld only on bits which are enabled by the ROMNRM Overlay Mask eld. See Section 11.4.12 for eld descriptions. 5.5.1. An Example
Figure 15 demonstrates the ingress switch APB priority interface, supposing that the ROF eld = 11001101, the ROM eld = 01111000, the ROL eld = 9, the IBOE bit is set, and that the current cell is a backward RM cell.
WRITE HERE IF CELL IS A BRM Byte #8 Switch Params #2 Byte #4 Switch Params #1 Byte #0 Switch Params #0 Byte #1 Byte #2 Byte #3 10 Byte #9 0 1 Byte #6 Byte #7 Byte #10 Byte #11
Byte #5
Figure 15. Example of Ingress Switch ABR Priority Interface 5.6. Egress Reset EFCI
The EREFNEgress Reset EFCI bit in the Context Parameters Extension Table for the connection to which the cell belongs is set. This feature can be used as part of Odestination behavior.O Egress Reset EFCI is enabled globally by the EPCVN Egress Features Enable bit in the ACR.
The MC92501 resets PTI[1] on a cell which meet the following conditions: Its PTI[2] = 0. It is a non-RM cell.
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SECTION 6. CLP TRANSPARENCY 6.1. Overview
header to IOCLPNIngress Overhead CLP bit in the cellOs overhead and assigns 0 to the header CLP. The cell is forwarded to the switch fabric. The switch fabric considers the cell as if it has CLP = 0. On the egress side, the MC92501 reconstructs the header CLP from the EOCLPNEgress Overhead CLP bit in the cellOs overhead. In order to support other applications, the MC92501 function is extended as follows. It assigns the ICTVNIngress CLP Transparency Value bit (dened in the Common Parameters Extension Word) to the cellOs header instead of 0. If the ICTVN Ingress CLP Transparency Value bit = 0 then we are back at the CLP transparency application. CLP Transparency is enabled globally by the IPCVNIngress Features Enable bit in the ACR register.
The trafc management specication denes two network operation models with relation to CLP = 1 ow: CLP transparent and CLP signicant. A connection which is CLP transparent does not have different Cell Loss Ratio (CLR) for CLP = 0 or CLP = 1 trafc, and therefore does not prefer discarding CLP = 1 over CLP = 0 cells on congestion. Current switch fabrics do distinguish globally between CLP = 0 trafc and CLP = 1 trafc with the CLP = 1 trafc being more susceptible to discarding in case of congestion. The MC92501 solves the problem in the following manner: If a cell belongs to a connection which supports CLP transparency (the ICTENIngress CLP Transparency Enable bit in the Common Parameters Extension Word is set), then the MC92501 moves the CLP from the cellOs
ICTVNIngress CLP Transparency Value NOTE 1 NOTE 2
Overhead
Header
Payload
Overhead
Header
Payload
Switch Fabric
MC92501 #1
MC92501 #2
NOTES: 1. If a cell belongs to a connection which supports CLP transparency (the ICTENIngress CLP Transparency Enable bit is set), then MC92501 moves the CLP from the cellOs header to the IOCLPNIngress Overhead CLP bit in the cellOs overhead and assigns the ICTVNIngress CLP Transparency Value bit to the header CLP. 2. If the CIFSNConnection Ingress Flow Status bit is set then the MC92501 reconstructs the header CLP from the EOCLPNEgress Overhead CLP bit in the cellOs overhead.
Figure 16. CLP Transparency with a CLP Significant Switch Fabric
The IOCLPNIngress Overhead CLP bit location is programmable using the OCBLNIOCLP Bit Location eld in the Ingress Switch Interface Conguration Register (ISWCR). The EOCLPNEgress Overhead bit location is programmable using the EOBYNEOCLP Byte Location eld and the EOBINEOCLP Bit Location eld in the Egress Switch Overhead Information Register 1 (ESOIR1).
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SECTION 7. INDIRECT EXTERNAL MEMORY ACCESS 7.1. Overview
7.2.2. Read Access
The MC92500 allows the processor to access its external memory for the duration of one cell processing time out of N, where N is programmable. The MC92501 will additionally allow the processor to access external memory while operating on the cell stream. The indirect access takes place at least once in every cell processing slot. The indirect access is not performed during maintenance.
7.2.
User Interface
Indirect external memory access is performed using two registers: the Indirect External Memory Access Address Register (IAAR) and the Indirect External Memory Access Data Register (IADR). 7.2.1. Write Access
In order to read from the external memory, the processor should poll the IABNIndirect External Memory Access Busy bit in the IAAR register to verify that it may write the IAAR register. If IAB is clear, then the processor can write the address, size, and direction into the appropriate registers. For a read operation, the IADNIndirect External Memory Address DIR bit is set to 1. Writing to the IAAR register triggers the MC92501 to wait for a dedicated clock, and read the data from external memory using the given address and write the data into the IADR register. Once the data was written into the IADR register, the MC92501 clears the IABNIndirect External Memory Access Busy bit in the IAAR register. The processor then may read the data from the IADR register. The address space which is covered by this interface includes all the non-destructive external memory access and an external address compression device. NOTE Indirect write access to an external memory space, which can be written by the MC92501, is not recommended. For example, an indirect write access to a ag-table record of an active connection is not recommended. It is advisable to use the maintenance cell slot for this purpose. Table 1 summarizes indirect access elds:
In order to write to the external memory, the processor should poll the IABNIndirect External Memory Access Busy bit in the IAAR register to verify the status of the IAAR and IADR registers. If IAB is clear, then the processor can write the address data and status into the appropriate registers. The IADNIndirect External Memory Address DIR bit is is set to 0 for a write operation. Writing to the IAAR register triggers the MC92501 to wait for a dedicated clock to write the data into the external memory using the given address and data. Once the MC92501 nishes writing, it clears the IABNIndirect External Memory Access Busy bit in the IAAR register.
Table 1. Indirect Access Fields
IADN Indirect External Memory Access DIR IAWN Indirect External Memory Access Size Least Signicant Bit of IAAN Indirect External Memory Access Address x 0 0 1 1 x DONData Order Function
0 0 0 0 0 1
0 1 1 1 1 x
x 0 1 0 1 x
Write IADR[31:00] to external memory word bits [31:00] Write IADR[31:16] to external memory word [31:16] Write IADR[15:00] to external memory word [15:00] Write IADR[15:00] to external memory word [15:00] Write IADR[31:16] to external memory word [31:16] Read external memory word bits [31:00] to IADR[31:00]
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SECTION 8. IMPROVED HOST INTERFACE 8.1. Overview
systems with less than three DMAs, each such DMA should switch between the MREQ lines. This switching can be done when using the MC92500 through the use of glue logic. In these cases, this feature enables a glueless interface. The MREQ signals default to the MC92500 conguration so that backwards compatibility is maintained. 8.1.3. Update the Definition of MWSH and MWSL Signals
In order to improve the MC92501 interface to the microprocessor, the following features were added: 8.1.1. An Additional MDTACK Signal
The MDTACK signals enable a glueless interface to systems on which there are two MDTACK signals and their combination conveys the bus width of the slave. The MDTACK1 signal is driven only when the MDTACK0 signal is driven and when the MDCNMDTACK Drive Control is set. 8.1.2. Programmable MREQ Signals
The MC92500 generates three DREQ signals: EMMREQ for external memory request, MCIREQ for cell insertion request, and MCOREQ for cell extraction request. The MC92501 changes the functionality (and the name) of the three DREQ lines. Each MREQ[n] line may be connected to each of the internal requests: external memory, cell insertion, or cell extraction. If a system contains three DMAs, then each DMA may be connected to a different DMA DREQ signal. In
MWSH and MWSL are used in MC92500 as word select during external memory accesses. Some systems assert these signals only during write cycles. The MC92501 uses these signals only on external memory write accesses. Read accesses are always performed regardless of these signals. Moreover, another use of these signals is for systems to use them for Address[1] bit and SIZE. The MC92501 supports another denition for the same pins: MWSH pin can serve as Address[1] while MWSL can serve as SIZE. The WSSMN Word Select Signals Mode bit selects which mode is supported. Table 2 describes the pinsO functionality:
Table 2. Host Interface Fields
WSSMNWord Select Signals Mode = 0 WSSMNWord Select Signals Mode = 1 and DONData Order = 0 A1 x 0 1 Size 0 1 1 WSSMNWord Select Signals Mode = 1 and DONData Order = 1 A1 x 1 0 Size 0 1 1 Write D(31:0) Write D(31:16) Write D(15:00) Function
MWSH 0 0 1
MWSL 0 1 0
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SECTION 9. EGRESS OVERHEAD MANIPULATION
The MC92501 supports the following features: The size of the ECI eld used by the egress cell processing block can be programmed by writing to the ECESNEgress Cell Processing Block ECI Size eld in the Egress Overhead Manipulation Register (EGOMR). The size of the MTTS eld used by the egress cell processing block can be programmed by writing to the ECTSNEgress Cell Processing Block MTTS Size eld in the EGOMR. The M bit used by the egress cell processing block can be either the M bit which was extracted from the cellOs overhead, the logical not of the M bit which was extracted from the cellOs overhead, or 1 or 0 by programming the ECMSNEgress Cell Processing Block M Bit Source eld in the EGOMR. In ECI on Header mode, the ECI is extracted from the ATM cell header. The header VPI eld size can be programmed to either 12 bits or 8 bits using the VPSNVPI Size in ECI on Header Mode bit of the Egress Switch Interface Conguration Register (ESWCR).
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SECTION 10. UTOPIA LEVEL 2 PHY INTERFACE
The MC92501 PHY interface can be programmed to support UTOPIA Level 2. It allows for operation of one TxClav and one RxClav signal. On the ingress direction, the MC92501 supports address polling on up to 16 physical links. It scans all the links in a round robin fashion and decides from which PHY to read the next cell. UTOPIA Level 2 is enabled on ingress by programming the IUMNIngress UTOPIA Mode bit of the Ingress PHY Conguration Register (IPHCR). In this mode, Receive PHY ID 0-3/Receive Address 0-3 (RXPHYID0-RXPHYID3/ RXADD0-RXADDR3) signals function as RXADDR0RXADDR4. NOTE RXADDR4 is a new functional signal in MC92501 that was a NC (No Connect) on the MC92500. UTOPIA Level 2 is enabled on egress by programming the EUMNEgress UTOPIA Mode bit of the Egress PHY Conguration Register (EPHCR). In this mode, the Transmit PHY ID 0-3 /Transmit Address 0-3 (TXPHYID0-TXPHYID3/ TXADDR0-TXADDR3) signals and the Transmit Next PHY ID Valid/Transmit Address 4 (TXPHYIDV/TXADDR4) signal are used as TXADDR0-TXADDR4. The MC92501 polls the link of the cell in its egress PHY IF FIFO, and when enabled it outputs the cell to the link PHY. The MC92501 performs address polling on all other links as well in order to enable external logic to monitor the PHYOs status. Figure 17 illustrates an application on which external logic monitors the RxClav signal while the MC92501 is polling the PHY devices. Based on this information, the external logic can input cells to the MC92501 egress ow.
PHY Device
PHY Device TxAddr MC92501
PHY Device
PHY Device TxAddr External Logic TxClav
Feedback
Figure 17. Feedback Using TxClav
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SECTION 11. REGISTER DESCRIPTIONS
This section describes the registers which were added or modied for the MC92501.
11.1.
General Register List
Table 3 contains all the registers which were added and their addresses. Table 3. General Register List
Register Group Register Name Mnemonic ADD (25:0) Ref. Page 25 25 26 26 32 33 34 33 33
Control Registers
Ingress Processing Control Register Egress Processing Control Register Indirect External Memory Access Address Register Indirect External Memory Access Data Register
IPLR EPLR IAAR IADR ESOIR1 RMOR EGOMR CPETP CTOR
0030824 0030828 0030810 0030814 0030818 003081C 0030820 0030d88 003082C
Conguration Register
Egress Switch Overhead Information Register 1 RM Overlay Register Egress Overhead Manipulation Register Common Parameters Extension Table Pointer Register CLP Transparency Overlay Register
11.2.
Status Reporting Registers
The following registers have been updated. The elds that have been added are in bold. 11.2.1. Interrupt Register (IR)
The FQF bit has been added.
31 OM 15 0 30 CM 14 0 29 MSE 13 UDI50 28 0 12 UDI40 27 0 11 UDI30 26 0 10 UDI20 25 0 9 UDI1ES PE 24 SPD 8 UDI0ES HE 23 0 7 0 22 0 6 0 21 FQF 5 0 20 CIQE 4 IPPE 19 CEQR 3 IPHE 18 CEQI 2 FQO 17 CEQL 1 FQEO 16 CEQF 0 MNAE
FQFNFMC Queue Full This bit reports that the internal FMC queue is full. The reason for this is that the FMC generation rate is higher then the allocated insertion bandwidth. Insertion rate is controlled by the insertion leaky bucket. 11.2.2. Interrupt Mask Register (IMR)
The FQFE bit has been added.
31 OME 15 0 30 CME 14 0 29 MSEE 13 28 0 12 27 0 11 26 0 10 25 0 9 UDIE1E SPEE 24 SPDE 8 UDIE0E SHEE 23 0 7 0 22 0 6 0 21 FQFE 5 0 20 CIQEE 4 IPPEE 19 CEQRE 3 IPHEE 18 CEQIE 2 FQOE 17 CEQLE 1 16 CEQFE 0
UDIE50 UDIE40 UDIE30 UDIE20
FQEOE MNAEE
FQFENFMC Queue Full Interrupt Enable When FQF and FQFE are set, an interrupt is generated.
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11.2.3.
ATMC CFB Revision Register (ARR)
The AMRV eld has been updated. Table 4. Values of ATMC CFB Revision Fields
AMRV 000001 ASRV 000000 ATMC CFB Revision MC92501 (MC92500 Revision B)
11.2.4.
MC92501 Revision Register (RR)
The MRV eld has been updated. Table 5. Values of the MC92501 Revision Fields
ID 10000000000000000000 MRV 000001 SRV 000000 MC92501 Revision MC92501 (MC92500 Revision B)
11.3.
Control Registers
The following registers have been added. 11.3.1. Ingress Processing Control Register (IPLR)
This register has the following structure:
31 0 15 0 30 0 14 0 29 0 13 0 28 0 12 0 27 0 11 0 26 0 10 0 25 0 9 0 24 0 8 0 23 0 7 0 22 0 6 0 21 0 5 0 20 0 4 0 19 0 3 0 18 0 2 0 17 0 1 ICNG 16 0 0 IAME
ICNGNGlobal Ingress Congestion Notication This bit noties the MC92501 whether there is congestion in the ingress ow. See Section 4. 0 = No ingress congestion. 1 = Ingress congestion. The MC92501 performs selective discard according to per-connection CIMENConnection Ingress Marking Enable bit. IAMENGlobal Ingress ABR Mark Enable This bit, when set, indicates that current ingress ow status implies that the MC92501 should perform RR marking and/or EFCI marking if enabled. See Section 5.4.1. 11.3.2. Egress Processing Control Register (EPLR) This register has the following structure:
31 0 15 0 30 0 14 0 29 0 13 0 28 0 12 0 27 0 11 0 26 0 10 0 25 0 9 0 24 0 8 0 23 0 7 0 22 0 6 0 21 0 5 0 20 0 4 0 19 0 3 0 18 0 2 0 17 0 1 0 16 0 0 EAME
EAMENGlobal Egress ABR Mark Enable This bit, when set, indicates that current egress ow status implies that the MC92501 should perform RR marking and/or EFCI marking if enabled. See Section 5.4.2.
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11.3.3.
Indirect External Memory Access Address Register (IAAR)
This register contains the address, width, and busy bit for accessing the MC92501 external memory or the external memory device. Refer to Section 7 for details. The register has the following structure:
31 IAB 15 30 IAD 14 29 IAW 13 28 0 12 27 0 11 26 0 10 9 25 IAAS 8 IAA 7 6 5 4 24 23 22 21 20 IAA 3 2 1 0 0 19 18 17 16
IABNIndirect External Memory Access Busy This bit indicates that indirect external memory access mechanism is busy. 0 = Indirect access mechanism is free and therefore indirect external memory access data register can be accessed. 1 = Indirect access mechanism is busy and therefore indirect access data register should not be accessed. IADNIndirect External Memory Access DIR This bit indicates indirect access direction. 0 = Indirect write access 1 = Indirect read access IAWNIndirect External Memory Access Size This bit indicates the size of the access. 0 = 32 bits 1 = 16 bits IAASNIndirect External Memory Access Address Space This eld indicates the accessed address space. 00 = Reserved 01 = External address compression device 10 = Non-destructive external memory 11 = Reserved IAANIndirect External Memory Access Address This eld indicates bits 23:1 of the address within the address space specied in the IAASNIndirect External Memory Access Address Space eld. 11.3.4. Indirect External Memory Access Data Register (IADR)
This register contains the data which should be written to the external memory in case of an indirect write access or the data that was last read from external memory in case of an indirect read access. Refer to Section 7 for details.
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11.4.
Configuration Register
The following registers have been updated. The elds that have been added are in bold. 11.4.1.
31 0 15
Ingress Processing Configuration Register (IPCR)
30 0 14 IPCC 29 0 13 28 0 12 0 27 0 11 IGZC 26 0 10 IUHC 25 0 9 IIP 24 0 8 IROE 23 IGCTE 7 0 22 ICCR 6 21 IRCR 5 IBCC 20 ISFCE 4 19 ISFNE 3 IPCV 18 ISPE 2 IAPE 17 ISBCE 1 16 ISBNE 0 IACE
IGCTENGlobal Ingress CLP Transparency Enable This bit enables CLP transparency function on the ingress. See Section 6 for details. ICCRNIngress Check CRC on RM Cells This bit determines whether the CRC of RM cells that are received in the ingress is checked. 0 = The CRC of RM cells that are recevied in the ingress is not checked. 1 = The CRC of RM cells that are received in the ingress is checked and if it is not okay, then the cell is removed and can be copied to the microprocessor. IRCRNIngress Recalculate CRC on RM Cells This bit determines whether the CRC of ingress RM cells is recalculated. 0 = The CRC of ingress RM cells is not recalculated. 1 = The CRC of ingress RM cells is recalculated. ISFCENGlobal Ingress Set FRM CI Enable This bit enables setting CI bit in forward RM cells received in ingress. See Section 5.4.3 for details. 0 = Setting CI bit in forward RM cells received in ingress is disabled. 1 = Setting CI bit in forward RM cells received in ingress is enabled. ISFNENGlobal Ingress Set FRM NI Enable This bit enables setting NI bit in forward RM cells received in ingress. See Section 5.4.3 for details. 0 = Setting NI bit in forward RM cells received in ingress is disabled. 1 = Setting NI bit in forward RM cells received in ingress is enabled. ISPENGlobal Ingress Set PTI Enable This bit enables setting PTI[1] bit in cells with PTI[2] = 0 which are received in ingress. See Section 5.4.3 for details. 0 = Setting PTI[1] bit in cells with PTI[2] = 0 which are received in ingress is disabled. 1 = Setting PTI[1] bit in cells with PTI[2] = 0 which are received in ingress is enabled. ISBCENGlobal Ingress Set BRM CI Enable This bit enables setting CI bit in backward RM cells received in ingress. See Section 5.4.3 for details. 0 = Setting CI bit in backward RM cells received in ingress is disabled. 1 = Setting CI bit in backward RM cells received in ingress is enabled. ISBNENGlobal Ingress Set BRM NI Enable This bit enables setting NI bit in backward RM cells received in ingress. See Section 5.4.3 for details. 0 = Setting NI bit in backward RM cells received in ingress is disabled. 1 = Setting NI bit in backward RM cells received in ingress is enabled. IROENIngress RM Overlay Enable This bit enables updating switch parameter words in the case of RM cells. See Section 5.5 for details. IPCVNIngress Features Enable This bit should be set when the following features are used: packet-based UPC, selective discard, and CLP transparency.
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MC92501 27
11.4.2.
31 0 15
Egress Processing Configuration Register (EPCR)
30 0 14 EPCC 29 0 13 28 0 12 0 27 0 11 0 26 0 10 0 25 0 9 EIP 24 0 8 0 23 EGCTE 7 0 22 ECCR 6 21 ERCR 5 EBCC 20 19 18 ESPE 2 RGFC 17 16
ESFCE ESFNE 4 3 EPCV
ESBCE ESBNE 1 0 0 0
EGCTENGlobal Egress CLP Transparency Enable This bit enables CLP transparency function on the egress. See Section 6 for details. ECCRNEgress Check CRC on RM Cells This bit determines whether the CRC of RM cells that are received in the egress is checked. 0 = The CRC of RM cells that are recevied in the egress is not checked. 1 = The CRC of RM cells that are received in the egress is checked and if it is not okay, then the cell is removed and can be copied to the microprocessor. ERCRNEgress Recalculate CRC on RM Cells This bit determines whether the CRC of egress RM cells is recalculated. 0 = The CRC of egress RM cells is not recalculated. 1 = The CRC of egress RM cells is recalculated. ESFCENGlobal Egress Set FRM CI Enable This bit enables setting CI bit in forward RM cells received in egress. See Section 5.4.2. 0 = Setting CI bit in forward RM cells received in egress is disabled. 1 = Setting CI bit in forward RM cells received in egress is enabled. ESFNENGlobal Egress Set FRM NI Enable This bit enables setting NI bit in forward RM cells received in egress. See Section 5.4.2. 0 = Setting NI bit in forward RM cells received in egress is disabled. 1 = Setting NI bit in forward RM cells received in egress is enabled. ESPENGlobal Egress Set PTI Enable This bit enables setting PTI[1] bit in cells with PTI[2] = 0 which are received in egress. See Section 5.4.2. 0 = Setting PTI[1] bit in cells with PTI[2] = 0 which are received in egress is disabled. 1 = Setting PTI[1] bit in cells with PTI[2] = 0 which are received in egress is enabled. ESBCENGlobal Egress Set BRM CI Enable This bit enables setting CI bit in backward RM cells received in egress. See Section 5.4.2. 0 = Setting CI bit in backward RM cells received in egress is disabled. 1 = Setting CI bit in backward RM cells received in egress is enabled. ESBNENGlobal Egress Set BRM NI Enable This bit enables setting NI bit in backward RM cells received in egress. See Section 5.4.2. 0 = Setting NI bit in backward RM cells received in egress is disabled. 1 = Setting NI bit in backward RM cells received in egress is enabled. EPCCNEgress Policing Counters Control This eld determines which counters appear in the Policing Counters Table if egress UPC is enabled. (The UPCFNUPC Flow bit in the ACR is set.) It also determines the size of each record in the table. 000 = The policing table does not exist. 001 = The policing table contains three counters and one reserved long word: DSCD0, DSCD1, TAG, Reserved. 010 = The policing table contains three counters: DSCD0, DSCD1, TAG. 011 = The policing table contains two counters: DSCD, TAG. 100 = The policing table contains one counter: TAG. 101 = The policing table contains one counter: DSCD. 110 = Reserved 111 = Reserved
MC92501 28
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EIPNEgress Insertion Priority This bit determines the priority between inserted/generated cells and egress received cells. Note that insertion is always limited by the leaky bucket mechanism. 0 = Inserted/generated cellsO priority is higher than egress received cells. 1 = Egress received cellsO priority is higher than inserted/generated cells. EPCVNEgress Features Enable This bit should be set when the reset EFCI feature is activated. See Section 5.6. 11.4.3.
31 ATC 15 UPCF 14 0 13 0
ATMC CFB Configuration Register (ACR)
30 29 SPC 12 0 28 27 COMC 11 0 26 INPC 10 0 25 EGPC 9 0 8 0 24 23 DVTC 7 0 6 0 22 21 FLGC 5 0 20 OAMC 4 0 19 VPRP 3 0 18 FTM 2 0 17 CRRP 1 0 16 PMAC 0 0
VPRPNVP RM Cell PTI This bit determines whether a cell is a VP RM cell only if its PTI = 6. 0 = A cell is a VP RM cell if and only if it belongs to a VP connection, its VCI = 6, and its PTI = 6. 1 = A cell is a VP RM cell if and only if it belongs to a VP connection and its VCI = 6. CRRPNVC RM Cell Removal Point This bit determines whether a VC cell whose PTI = 6 or 7 is removed at the OAM termination point, or whether its removal is subjected to the per-connection enable bits for PTI = 6 or PTI = 7. 0 = A VC cell whose PTI = 6 or 7 is removed at the OAM termination point as dened by the EEOTNEgress End-to-End OAM Termination bit in the egress and by the IEOTNIngress End-to-End OAM Termination bit in the ingress. 1 = A VC cell is removed at the egress if the EP6RNEgress PTI 6 Remove bit is set and its PTI = 6 or if the EP7RNEgress PTI 7 Remove bit is set and its PTI = 7. A VC cell is removed at the ingress if the IP6RNIngress PTI 6 Remove bit is set and its PTI = 6 or if the IP7RNIngress PTI 7 Remove bit is set and its PTI = 7. PMACNPM on All Connections This bit determines whether the OAM performance monitoring test can be done on all connections or on 64 connections. 0 = Performance monitoring can be done only on 64 selected connections. 1 = Performance monitoring can be done on all connections. UPCFNUPC Flow This bit determines whether the UPC is active in the ingress ow or in the egress ow. 0 = The UPC is active in the ingress ow. 1 = The UPC is active in the egress ow. 11.4.4.
31 EIAS 15
Egress Switch Interface Configuration Register (ESWCR)
30 EEAS 14 29 VPS 13 ESNB 28 0 12 27 0 11 26 IHAF 10 0 25 0 9 24 ESFC 8 23 EFE 7 IMSB 22 MTSE 6 21 EATD 5 20 ELNS 4 19 ESPC 3 18 ESPR 2 ILSB 17 EPLP 1 16 ESHF 0
EIASNGlobal IFS Enable This bit enables the MC92501 to use theIFSNOverhead Ingress Flow Status bit in the egress switch overhead. See Section 5.4.1 for details. 0 = The IFSNOverhead Ingress Flow Status bit is not dened in the egress overhead elds so it cannot trigger ABR cell marking. 1 = The IFSNOverhead Ingress Flow Status bit is dened in the egress overhead elds and is used by the MC92501 for marking cells.
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MC92501 29
EEASNGlobal EFS Enable This bit enables the MC92501 to use the EFSNOverhead Egress Flow Status bit in the egress switch overhead. See Section 5.4.2 for details. 0 = The EFSNOverhead Egress Flow Status bit is not dened in the egress overhead elds so it cannot trigger ABR cell marking. 1 = The EFSNOverhead Egress Flow Status bit is dened in the egress overhead elds and is used by the MC92501 for marking cells. VPSNVPI Size in ECI on Header Mode This bit determines the size of the VPI eld for ECI on Header mode (IHAF = 1). See Section 9 for details. 0 = VPI size is 12 bits 1 = VPI size is 8 bits 11.4.5. Egress Switch Overhead Information Register 0 (ESOIR0)
This register name was ESOIR on MC92500. The following denition is changed: MTBI-MTTS Bit Location This eld indicates the location of the MTTS eld within the byte specied by the MTBY-MTTS Byte Location eld. 0 = MTTS equals the value that resides in bits 7:5 of the byte pointed to by the MTBY-MTTS Byte Location eld. 1 = MTTS equals the value that resides in bits 7:6 of the byte pointed to by the MTBY-MTTS Byte Location eld. 2 = MTTS equals the value that resides in bit 7 of the byte pointed to by the MTBY-MTTS Byte Location eld. 3 = MTTS equals the value that resides in bits 3:0 of the byte pointed to by the MTBY-MTTS Byte Location eld. 4 = MTTS equals the value that resides in bits 4:1 of the byte pointed to by the MTBY-MTTS Byte Location eld. 5 = MTTS equals the value that resides in bits 5:2 of the byte pointed to by the MTBY-MTTS Byte Location eld. 6 = MTTS equals the value that resides in bits 6:3 of the byte pointed to by the MTBY-MTTS Byte Location eld. 7 = MTTS equals the value that resides in bits 7:4 of the byte pointed to by the MTBY-MTTS Byte Location eld. Note that this denition is backwards-compatible to the denition in MC92500. 11.4.6.
31 DO 15 0
Microprocessor Configuration Register (MPCONR)
30 0 14 0 13 MDC 29 28 0 12 0 27 0 11 DDDS 26 WSSM 10 0 25 0 9 DDGR 24 0 8 7 0 23 RQ0 6 DDEM 22 21 0 5 4 0 20 RQ1 3 DDCI 19 18 0 2 0 1 DDCE 17 RQ2 0 16
WSSMNWord Select Signals Mode This bit denes the functionality of the MP Word Write Enable High / Address 1 (MWSH/A1) and the MP Word Write Enable Low / SIZE (MWSL/SIZE) signals. See Section 8.1.3 for details. 0 = MWSH/A1 functions as MWSH-word write enable high and MWSL/SIZE functions as MWSL-word write enable low. 1 = MWSH/A1 functions as A1 and MWSL/SIZE functions as SIZE. RQ0NMREQ0 Signal Functionality This eld denes the functionality of the MP Request 0 (MREQ0) signal. See Section 8.1.2 for details. 00 = Cell in request 01 = Cell in request 10 = Cell out request 11 = External memory request RQ1NMREQ1 Signal Functionality This eld denes the functionality of the MP Request 1 (MREQ1) signal. See Section 8.1.2 for details. 00 = Cell out request 01 = Cell in request 10 = Cell out request 11 = External memory request
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MOTOROLA
RQ2NMREQ2 Signal Functionality This eld denes the functionality of the MP Request 2 (MREQ2) signal. See Section 8.1.2 for details. 00 = External memory request 01 = Cell in request 10 = Cell out request 11 = External memory request MDCNMDTACK Drive Control This bit determines which MDTACK signals are driven. 0 = MDTACK0 is driven and MDTACK1 is not driven. 1 = Both MDTACK0 and MDTACK1 are driven. 11.4.7. Maintenance Configuration Register (MACONR)
The MSDR eld is expanded from 6 bits to 9 bits.
31 0 15 30 0 14 29 0 13 28 0 12 27 0 11 MSDR 26 0 10 25 0 9 24 0 8 23 0 7 22 0 6 0 21 0 5 20 0 4 19 0 3 MSIR 18 0 2 17 0 1 16 0 0
The maximum value for the MSDR is therefore 511 instead of 63. This means that the maintenance request signals can be asserted as much as 511 clocks (or 8 cell processing slots) before the CM bit. 11.4.8.
31 0 15 0
Ingress PHY Configuration Register (IPHCR)
30 0 14 0 29 0 13 0 28 0 12 0 27 0 11 0 26 0 10 0 25 0 9 0 24 0 8 0 23 0 7 0 22 0 6 0 21 0 5 0 20 0 4 IUM 19 0 3 INVPD 18 0 2 IPOM 17 0 1 IPPR 16 0 0 IPLP
IUMNIngress UTOPIA Mode This bit denes the UTOPIA level mode of the ingress PHY. See Section 10. 0 = UTOPIA Level 1 1 = UTOPIA Level 2 11.4.9.
31 0 15 0
Egress PHY Configuration Register (EPHCR)
30 0 14 0 29 0 13 0 28 0 12 0 27 0 11 0 26 0 10 0 25 0 9 0 24 0 8 0 23 0 7 0 22 0 6 0 21 0 5 0 20 0 4 EUM 19 0 3 EPFC 18 0 2 EPOM 17 0 1 ECGE 16 0 0 EGIC
EUMNEgress UTOPIA Mode This bit denes the UTOPIA level mode of the egress PHY. See Section 10. 0 = UTOPIA Level 1 1 = UTOPIA Level 2
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MC92501 31
11.4.10.
31 0 15 0
MC92501 General Configuration Register (GCR)
30 0 14 0 29 0 13 0 28 0 12 0 27 0 11 0 26 0 10 0 25 0 9 0 24 0 8 0 23 0 7 0 22 0 6 CMPC 21 0 5 0 20 0 4 0 19 0 3 ILCC 18 0 2 0 17 0 1 0 16 PHIDC 0 ELCC
CMPCNContext Parameters Extension Table Control This bit determines the existence of the Context Parameters Extension Table in external memory. See Section 12.1 for details. 0 = The Common Parameters Table does not exist. 1 = The Common Parameters Table exists. 11.4.11. Egress Switch Overhead Information Register 1 (ESOIR1)
This register determines the location of the overhead information in the data structure received from the switch. The register has the following structure:
31 0 15 30 0 14 29 0 13 EIBY 28 0 12 27 0 11 26 0 10 25 0 9 EIBI 24 0 8 7 6 23 22 21 EOBY 5 EEBY 4 3 2 20 19 18 17 EOBI 1 EEBI 0 16
EOBYNEOCLP Byte Location This eld contains the byte number of the switch data structure in which the EOCLPNEgress Overhead CLP bit in the cellOs overhead. The byte on which STXSOC is asserted is byte number 0. See Section 6 for details. EOBINEOCLP Bit Location This eld contains the number of the EOCLPNEgress Overhead CLP bit in the cellOs overhead. The most signicant bit is number 7, and the least signicant bit is number 0. See Section 6 for details. EIBYNIFS Byte Location This eld contains the byte number of the switch data structure in which the IFSNOverhead Ingress Flow Status bit can be found (overhead, header, and HEC bytes). The byte on which STXSOC is asserted is byte number 0. See Section 5.4.1.2 for details. EIBINIFS Bit Location This eld contains the number of the IFSNOverhead Ingress Flow Status bit within the byte specied by the EEBYNEFS Byte Location eld. The most signicant bit is number 7, and the least signicant bit is number 0. See Section 5.4.1.2 for details. EEBYNEFS Byte Location This eld contains the byte number of the switch data structure in which the EFSNOverhead Egress Flow Status bit can be found (overhead, header, and HEC bytes). The byte on which STXSOC is asserted is byte number 0. See Section 5.4.2.2 for details. EEBINEFS Bit Location This eld contains the number of the EFSNOverhead Egress Flow Status bit within the byte specied by the EIBYNIFS Byte Location eld. The most signicant bit is number 7, and the least signicant bit is number 0. See Section 5.4.2.2 for details.
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11.4.12.
RM Overlay Register (RMOR)
This register contains all the parameters which are related to RM cell overlay. Refer to Section 5.5 for details. The register has the following structure:
31 IBOE 15 0 30 IFOE 14 0 29 0 13 0 28 0 12 0 11 0 10 0 27 26 ROL 9 0 8 0 7 6 5 4 ROF 25 24 23 22 21 20 ROM 3 2 1 0 19 18 17 16
IBOENIngress BRM Overlay Enable This bit determines whether the MC92501 overlays the ROFNRM Overlay eld on the switch parameters for ingress backward RM cells. 0 = Switch parameters are not overlayed when a backward RM cell is received in the ingress. 1 = Switch parameters are overlayed when a backward RM cell is received in the ingress. IFOENIngress FRM Overlay Enable This bit determines whether the MC92501 overlays the ROFNRM Overlay eld on the switch parameters for ingress forward RM cells. 0 = Switch parameters are not overlayed when a forward RM cell is received in the ingress. 1 = Switch parameters are overlayed when a forward RM cell is received in the ingress. ROLNRM Overlay Location This eld contains the number of the switch parameters byte which should be overlayed. ROMNRM Overlay Mask This eld contains the byte mask which serves for overlaying the ROFNRM Overlay eld over the ingress switch parameters byte. ROFNRM Overlay This eld contains the byte which is overlayed on the ingress switch parameters byte. Each bit in this eld is overlayed on the corresponding bit in the ingress switch parameters only if it is enabled by the corresponding bit in the ROMNRM Overlay Mask eld. 11.4.13. CLP Transparency Overlay Register (CTOR)
This register contains the location of the IOCLPNIngress Overhead CLP bit in the ingress switch parameters. See Section 6 for details. The register has the following structure:
31 0 15 0 30 0 14 0 29 0 13 0 28 0 12 0 27 0 11 0 26 0 10 0 25 0 9 0 24 0 8 0 23 0 7 0 22 0 6 21 0 5 OCBI 20 0 4 19 0 3 18 0 2 OCBL 17 0 1 16 0 0
OCBLNIOCLP Byte Location This eld contains the byte number within the switch parameter word on which the IOCLPNIngress Overhead CLP bit is located. The most signicant byte is number 0, and the least signicant byte is number 3. OCBINIOCLP Bit Location This eld contains the number of the IOCLPNIngress Overhead CLP bit within the byte specied by the OCBLNIOCLP Byte Location eld. The most signicant bit is number 7, and the least signicant bit is number 0. 11.4.14. Context Parameters Extension Table Pointer Register (CPETP)
This register contains the pointer to the rst word of the Context Parameters Extension Table. The pointer is in units of 256 bytes.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
CEPTP
0
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MC92501 33
11.4.15.
Egress Overhead Manipulation Register (EGOMR)
This register contains elds for manipulating egress overhead elds. See Section 9 for details.
31 0 15 0 30 0 14 0 29 0 13 0 28 0 12 0 27 0 11 0 26 0 10 0 25 0 9 0 24 0 8 0 23 0 7 ECMS 22 0 6 21 0 5 ECTS 20 0 4 19 0 3 18 0 2 ECES 17 0 1 16 0 0
ECMSN Egress Cell Processing Block M Bit Source This eld contains the source for the M bit which is used by the egress cell processing block. 00 = The M bit used by the egress cell processing block is taken from the M bit which is extracted from the switch cell data structure. 01 = The M bit used by the egress cell processing block is taken from the logical NOT of the M bit which is extracted from the switch cell data structure. 10 = The M bit used by the egress cell processing block is 0. 11 = The M bit used by the egress cell processing block is 1. ECTSN Egress Cell Processing Block MTTS Size This eld contains the size of the MTTS eld which is used by the egress cell processing block. 0 = The MTTS eld which is used by the egress cell processing block is the MTTS eld, which is extracted from the switch cell data structure. 1 = The MTTS eld which is used by the egress cell processing block is the least signicant bit of the MTTS eld, which is extracted from the switch cell data structure. 2 = The MTTS eld which is used by the egress cell processing block is the two least signicant bits of the MTTS eld, which are extracted from the switch cell data structure. 3 = The MTTS eld which is used by the egress cell processing block is the three least signicant bits of the MTTS eld, which are extracted from the switch cell data structure. ECESN Egress Cell Processing Block ECI Size This eld contains the size of the ECI eld which is used by the egress cell processing block. 0 = The ECI eld which is used by the egress cell processing block is the ECI eld, which is extracted from the switch cell data structure. 1 = Reserved 2 = Reserved 3 = Reserved 4 = Reserved 5 = Reserved 6 = The ECI eld which is used by the egress cell processing block is the six least signicant bits of the ECI eld, which are extracted from the switch cell data structure. 7 = The ECI eld which is used by the egress cell processing block is the seven least signicant bits of the ECI eld, which are extracted from the switch cell data structure. 8 = The ECI eld which is used by the egress cell processing block is the eight least signicant bits of the ECI eld, which are extracted from the switch cell data structure. 9 = The ECI eld which is used by the egress cell processing block is the nine least signicant bits of the ECI eld, which are extracted from the switch cell data structure. 10 = The ECI eld which is used by the egress cell processing block is the 10 least signicant bits of the ECI eld, which are extracted from the switch cell data structure. 11 = The ECI eld which is used by the egress cell processing block is the 11 least signicant bits of the ECI eld, which are extracted from the switch cell data structure. 12 = The ECI eld which is used by the egress cell processing block is the 12 least signicant bits of the ECI eld, which are extracted from the switch cell data structure. 13 = The ECI eld which is used by the egress cell processing block is the 13 least signicant bits of the ECI eld, which are extracted from the switch cell data structure. 14 = The ECI eld which is used by the egress cell processing block is the 14 least signicant bits of the ECI eld, which are extracted from the switch cell data structure. 15 = The ECI eld which is used by the egress cell processing block is the 15 least signicant bits of the ECI eld, which are extracted from the switch cell data structure.
MC92501 34
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SECTION 12. EXTERNAL MEMORY DESCRIPTION
The following table has been added.
12.1.
Context Parameters Extension Table
Each context Parameters Extension Table record contains one word, the Common Parameters Extension Word. 12.1.1.
31
Common Parameters Extension Word
30 29 28 27 26 25 24 23 22 21 0 9 EREF 8 0 7 ISDM 6 5 UOM 20 0 4 19 CIFS 3 0 18 CEFS 2 ICTV 17 ECTE 1 ICTE 16 CEME 0 CIME
BKPT[21:12] 15 0 14 13 PDV 12 11 0 10 0
BKPT[21:12]NBucket Pointer[21:12] When VPAP-VP on all connections, this eld contains bits 21 to 12 of the bucket point. When VPAP-VP on all connections is reset, this eld is reserved and should be 0. CIFSNConnection Ingress Flow Status The MC92501 copies the IFSNOverhead Ingress Flow Status bit to this bit. This bit is used by the ingress processing block for ABR cell marking. This bit is therefore intended for the MC92501Os internal use. See Section 5.4.1 for details. CEFSNConnection Egress Flow Status The MC92501 copies the EFSNOverhead Egress Flow Status bit to this bit. This bit is used by the ingress processing block for ABR cell marking. This bit is therefore intended for the MC92501Os internal use. See Section 5.4.2 for details. ECTENEgress CLP Transparency Enable This bit determines whether CLP should be copied from the EOCLPNEgress Overhead CLP bit in the cellOs overhead bit to the cell header. See Section 6 for details. 0 = CLP should not be copied from the switch overhead to the cell header. 1 = CLP should be copied from the switch overhead to the cell header. CEMENConnection Egress Marking Enable This bit enables marking of cells which are received in the egress. See Section 5.4.2. 0 = Marking of cells which are received in the egress is disabled. 1 = Marking of cells which are received in the egress is enabled. IPDVNIngress Packet Discard Variables This eld is accessed only by the MC92501. EREFNEgress Reset EFCI This bit determines if PTI[1] of an egress cell is to be reset. 0 = PTI[1] of an egress cell is not reset. 1 = PTI[1] of an egress cell is to be reset. ISDMNIngress Selective Discard Operation Mode This eld determines the selective discard operation mode. See Section 3. 00 = No selective discard. 01 = Reserved. 10 = Selective discard on CLP = 1 ow. 11 = Selective discard on CLP = 0+1 ow. UOMNUPC Operation Mode This eld determines the UPC operation mode. 00 = Cell-based UPC 01 = Partial Packet Discard (PPD). See Section 3.3 for details. 10 = Early Packet Discard (EPD). See Section 3.4 for details. 11 = Limited EPD. SeeSection 3.5 for details.
MOTOROLA
MC92501 35
ICTVNIngress CLP Transparency Value This bit determines the value that should be written to a cellOs header if the ICTENIngress CLP Transparency Enable bit is set. See Section 6 for details. ICTENIngress CLP Transparency Enable This bit determines whether CLP should be copied to the IOCLPNIngress Overhead CLP bit and whether the ICTVNIngress CLP Transparency Value bit should be written to the cell header CLP. See Section 6 for details. 0 = The ingress header CLP bit is not touched. 1 = CLP should be copied from the cell header to the ingress switch parameters. The ICTVNIngress CLP Transparency Value bit should be written to the cell header CLP. CIMENConnection Ingress Marking Enable This bit enables marking of cells which are received in the ingress. See Section 5.4.3 for details. 0 = Marking of cells which are received in the ingress is disabled. 1 = Marking of cells which are received in the ingress is enabled.
12.2.
CONTEXT PARAMETERS TABLE
Some bits have been added, and some bit denitons have been updated in the Egress Parameters Word and the Ingress Parameters Word. These bits are in bold. 12.2.1.
31 ECIV 15 ESAI
Egress Parameters
30 EVPC 14 ESRD 29 EEOT 13 ESCS 28 ESOT 12 ESCE 27 ESOO 11 ECA 26 Rsvd 10 ERA 25 ECAS 9 EP6C 24 ECRD 8 EP7C 23 ECOT 7 EVRE 22 ECAO 6 EP6R 21 ECSF 5 EP7R 20 ECEF 4 19 ECSB 3 18 ECEB 2 Reserved 17 Rsvd 1 16 Rsvd 0
EP6RNEgress PTI 6 Remove When this bit is set and the CRRP-VC RM cell removal point is set, then an egress cell whose PTI = 6 is removed, provided that the connection is a VC connection. EP7RNEgress PTI 7 Remove When this bit is set and the RRP-RM cell removal point is set, then an egress cell whose PTI = 7 is removed, provided that the connection is a VC connection. EEOTNEgress End-to-End OAM Termination When this bit is set, the egress ow is treated as the terminating point of the OAM end-to-end cell ow for the connection. Additionally, if the CRRPNVC RM Cell Removal Point bit is reset, then cells with PTI = 6 or 7 are removed at this point. 12.2.2.
31 ICIV 15 ISAI
Ingress Parameters:
30 IVPC 14 ISRD 29 IEOT 13 ISCS 28 ISOT 12 ISCE 27 ISOO 11 ICA 26 Rsvd 10 IRA 25 ICAS 9 IP6C 24 ICRD 8 IP7C 23 ICOT 7 IVRE 22 ICAO 6 IP6R 21 ICSF 5 IP7R 20 ICEF 4 19 ICSB 3 18 ICEB 2 Reserved 17 Rsvd 1 16 Rsvd 0 UDT
IP6RNIngress PTI 6 Remove When this bit is set and the RRP-RM Cell Removal Point is set, then an ingress cell whose PTI = 6 is removed, provided that the connection is a VC connection. IP7RNIngress PTI 7 Remove When this bit is set and the RRP-RM Cell Removal Point is set, then an ingress cell whose PTI = 7 is removed, provided that the connection is a VC connection. IEOTNIngress End-to-End OAM Termination When this bit is set, the ingress ow is treated as the terminating point of the OAM end-to-end cell ow for the connection. Additionally, if the CRRPNVC RM Cell Removal Point bit is reset, then cells which belong to a VC connection and whose PTI = 6 or 7 are removed at this point.
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12.2.3.
Common Parameters
The size and the location of some of the elds is changed according to PMAC-PM on all connections. When VPAP-VP on all connections is reset, the structure of the common parameters is the structure of the MC92500.
31 IOPV 15 30 EOPV 14 13 12 29 28 27 26 25 24 23 NBK 9 8 7 6 5 4 22 21 20 19 18 17 16
OAM_ptr[5:0] 11 10
BKT_PTR(21:16) 3 2 1 0
BKT_ptr(15:0)
When PMAC-PM on all connections is set, the structure is as follows:
31 IOPV 15 30 EOPV 14 13 29 NBK 12 11 10 9 8 7 28 27 26 25 24 23 22 21 20 19 18 17 16
BKT_PTR(11:00) 6 5 4 3 2 1 0
OAM_Ptr(15:0)
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MC92501 37
SECTION 13. DATA STRUCTURES
This section presents the data structures which where added or updated.
13.1.
13.1.1.
General Fields
Reason
The denition of Reason 01001 is changed: OA CRC error was detectedO instead of OA CRC error was detected (OAM cells only)O.
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SECTION 14. SIGNAL DESCRIPTION
The following are the pins which have been added or whose denition has been changed. MP Request 1 (MREQ1) This output signal can be programmed to one of the above three options. Its default value is the second option: MP Cell Out Request (MCOREQ). See Section 8.1.2 and Section 11.4.6 for details. MP Request 2 (MREQ2) This output signal can be programmed to one of the above three options. Its default value is the third option: External Memory Maintenance Request (EMMREQ). See Section 8.1.2 and Section 11.4.6 for details. NOTE The default values of MREQ0, MREQ1, and MREQ2 signals are MCIREQ, MCOREQ, and EMMREQ, respectively. These default values make the MC92501 backwards-compatible with the MC92500. MP Word Write Enable High / Address 1 (MWSH/A1) This input signal can be programmed by the WSSMNWord Select Signals Mode bit to one of the following modes: 1. Write-Enable Mode: This signal indicates that the high word is being written. During a maintenance write access, the value detected on MWSH/A1 is driven on the appropriate EMBSH signal. During the read access, the EMBSH signal is always asserted. This signal is active low. 2. Add1-Size Mode: This signal serves as address 1 during a maintenance write access. During a read access, this signal is ignored. This signal is sampled by the MC92501 on the falling edge of MCLK. See Section 8.1.3 and Section 11.4.6 for details. MP Word Write Enable Low / SIZE (MWSL/SIZE) This input signal can be programmed by the WSSMNWord Select Signals Mode bit to one of the following modes: 1. Write-Enable Mode: This signal indicates that the low word is being written. During a maintenance write access, the value detected on MWSL/SIZE is driven on the appropriate EMBSL signal. During the read access, the EMBSL signal is always asserted. This signal is active low. 2. Add1-Size Mode: This signal indicates the size of the maintenance write access which is either 32-bit or 16-bit access. During a read access, this signal is ignored and the access width is 32 bits. This signal is sampled by the MC92501 on the falling edge of MCLK. See Section 8.1.3 and Section 11.4.6 for details. NOTE All cell extraction register, cell insertion register, and general register accesses are long-word (32bit) accesses, so both MWSH/A1 and MWSL/ SIZE should be asserted low for these write accesses when write-enable mode is selected.
14.1.
Microproccessor Signals (MP)
The following signal denitions have been updated. The MC92500 MDTACK signal is renamed to MP Data Acknowledge0 (MDTACK0) and the MP Data Acknowledge0 (MDTACK1) signal has been added. MP Data Acknowledge0 (MDTACK0), MP Data Acknowledge1 (MDTACK1) MDTACK0 and MDTACK1 are three-state output signals used to indicate when the data on MDATA is valid during a read access from the MC92501. At the end of each access, these signals are actively pulled up and then released. The user may program the MC92501 not to drive these signals during certain types of accesses. See Section 11.4.6 for details. These signals are active low and the outputs are asynchronous to the MCLK. MP Cell Request Options MREQ0, MREQ1, and MREQ2 signals replace MCIREQ, MCOREQ, and EMMREQ, respectively. Each of the MREQ[n] signals are programmable to one of the following options: 1. MP Cell In Request MREQ[n] is an output signal that can be used by an external DMA device as a control line indicating when to start a new cell insertion cycle into the MC92501. It is asserted whenever the cell insertion register array is available to be written. This signal is active low, and the output is on the falling edge of MCLK. 2. MP Cell Out Request MREQ[n] is an output signal that may be used by an external DMA device as a control line indicating when to start a new cell extraction cycle from the MC92501. It is asserted whenever the cell extraction register array is available to be read. The microprocessor control register (MPCTLR) contains the number of maintenance accesses performed in a single maintenance slot. It is active low, and the output is on the falling edge of MCLK. 3. External Memory Maintenance Request MREQ[n] is an output signal that can be asserted a programmable number of clock cycles before the start of an external memory maintenance cycle (see Section 11.4.7). It is negated after a programmable number of maintenance accesses have been performed. It is active low, and the output is on the falling edge of MCLK. MP Request 0 (MREQ0) This output signal can be programmed to one of the above three options. Its default value is the rst option: MP Cell In Request (MCIREQ). See Section 8.1.2 and Section 11.4.6 for details.
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MC92501 39
14.2.
Ingress PHY Signals
The denition of RXPHYID0-3 has been updated. The RXADDR4 signal has been added. Receive PHY ID 0-3/Receive Address 0-3 (RXPHYID0RXPHYID3/RXADDR0RXADDR3) This bus has two modes depending on the IUMNIngress UTOPIA Mode bit of the Ingress PHY Conguration Register (IPHCR): In UTOPIA Level 1 N The RXPHYID0RXPHYID3 input bus indicates the ID number of the PHY device currently transferring data to the MC92501. If only a single PHY device is supported, this bus should be tied low. This bus is sampled along with the rst octet of each cell. In UTOPIA Level 2 N The RXADD0RXADDR3 output bus that indicates the four least signicant bits of the ID number of the PHY device which is being polled or selected by the MC92501. See Section 10 for details. Receive Address 4 (RXADDR4) This signal is an output signal that indicates the most signicant bit of the ID number of the PHY device which is being polled or selected by the MC92501. See Section 10 for details.
Transmit PHY ID 0-3 / Transmit Address 0-3 (TXPHYID0TXPHYID3/TXADDR0TXADDR3) This bus has two modes depending on the EUMNEgress UTOPIA Mode bit: In UTOPIA Level 1 N The TXPHYID0TXPHYID3 output bus indicates the ID number of the PHY device to which either the current cell or the next cell is directed. The functionality is controlled by the MC92500 General Conguration Register (GCR). In UTOPIA Level 2 N The TXADDR0TXADDR3 output bus indicates the four less signicant bits of the ID number of the PHY device which is being polled or selected by the MC92501. See Section 10 for details. Transmit Next PHY ID Valid/Transmit Address 4 (TXPHYIDV/TXADDR4) This bit has two modes depending on the EUMNEgress UTOPIA Mode bit: In UTOPIA Level 1 N The TXPHYIDV output signal, when low, indicates that TXPHYID (when congured as the next cellOs ID) is valid. If TXPHYID is congured to refer to the current cell, TXPHYIDV is not used. In UTOPIA Level 2 N The TXADDR4 output signal indicates the most signicant bit of the ID number of the PHY device which is being polled or selected by the MC92501. See Section 10 for details.
14.3.
Egress PHY Signals
The TXPHYID0-3 denition has been updated and renamed to TXPH. TXPHYIDV/TXADDR4 signal replaces TXPHYIDV signal of the MC92500.
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SECTION 15. TEST OPERATION 15.1. Device Identification Register
The code for the MC92501 is changed to: 0100_0001_1100_0011_1010_0000_0001_1101.
15.2.
Boundary Scan Register
Table 6. Boundary Scan Bit Denition Signal Name
STXCLK STXCLAV STXSOC STXPRTY STXDATA7 STXDATA6 STXDATA5 STXDATA4 STXDATA3 STXDATA2 STXDATA1 STXDATA0 STXENB TXENB TXFULL TXCCLR TXPHYIDV TXPRTY TXSOC TXDATA7 TXDATA6 TXDATA5 TXDATA4 TXDATA3 TXDATA2 TXDATA1 TXDATA0 TXPHYID3
I/O Cell Type
in bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir in bidir three-state bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir three-state
System Mode
in out in in in in in in in in in in in out in in out out out out out out out out out out out out
Scan Bit #
360 359 357 355 353 351 349 347 345 343 341 339 337 335 333 332 330 329 327 325 323 321 319 317 315 313 311 309 328 326 324 322 320 318 316 314 312 310 331 358 356 354 352 350 348 346 344 342 340 338 336 334
Output Enable
TXPHYID2
TXPHYID1
three-state
three-state
out
out
308
307
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MC92501 41
Table 6. Boundary Scan Bit Denition Signal Name
TXPHYID0 MDATA31 MDATA30 MDATA29 MDATA28 MDATA27 MDATA26 MDATA25 MDATA24 MDATA23 MDATA22 MDATA21 MDATA20 MDATA19 MDATA18 MDATA17 MDATA16 MDATA15 MDATA14 MDATA13 MDATA12 MDATA11 MDATA10 MDATA9 MDATA8 MDATA7 MDATA6 MDATA5 MDATA4 MDATA3 MDATA2 MDATA1
I/O Cell Type
three-state bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir
System Mode
out bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir
Scan Bit #
306 305 303 301 299 297 295 293 291 289 287 285 283 281 279 277 275 273 271 269 267 265 263 261 259 257 255 253 251 249 247 245 304 302 300 298 296 294 292 290 288 286 284 282 280 278 276 274 272 270 268 266 264 262 260 258 256 254 252 250 248 246 244
Output Enable
enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1 enscan1
MDATA0
MADD25
bidir
bidir
bidir
in
243
241
242
240
enscan1
MC92501 42
MOTOROLA
Table 6. Boundary Scan Bit Denition Signal Name
MADD24 MADD23 MADD22 MADD21 MADD20 MADD19 MADD18 MADD17 MADD16 MADD15 MADD14 MADD13 MADD12 MADD11 MADD10 MADD9 MADD8 MADD7 MADD6 MADD5 MADD4 MADD3 MADD2 MSEL MREQ0 MREQ1 MDTACK0 MINT MREQ2 MCLK MWR MWSH
I/O Cell Type
bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir in three-state three-state three-state three-state three-state in in in
System Mode
in in in in in in in in in in in in in in in in in in in in in in in in out out three-state out out in in in
Scan Bit #
239 237 235 233 231 229 227 225 223 221 219 217 215 213 211 209 207 205 203 201 199 197 195 193 192 191 190 189 188 187 186 185 238 236 234 232 230 228 226 224 222 220 218 216 214 212 210 208 206 204 202 200 198 196 194
Output Enable
enscan2
MWSL
MDS
in
in
in
in
184
183
MOTOROLA
MC92501 43
Table 6. Boundary Scan Bit Denition Signal Name
SRXENB SRXDATA7 SRXDATA6 SRXDATA5 SRXDATA4 SRXDATA3 SRXDATA2 SRXDATA1 SRXDATA0 SRXCLK SRXCLAV SRXSOC SRXPRTY MDTACK1 RXADDR4 RXSOC RXENB RXEMPTY RXPHYID3 RXPHYID2 RXPHYID1 RXPHYID0 RXPRTY RXDATA7 RXDATA6 RXDATA5 RXDATA4 RXDATA3 RXDATA2 RXDATA1 RXDATA0 EMDATA31
I/O Cell Type
in bidir bidir bidir bidir bidir bidir bidir bidir in bidir bidir bidir three-state three-state bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir
System Mode
in three-state three-state three-state three-state three-state three-state three-state three-state in out three-state three-state three-state three-state in out in bidir bidir bidir bidir in in in in in in in in in bidir
Scan Bit #
182 181 179 177 175 173 171 169 167 165 164 162 160 158 157 156 154 152 150 148 146 144 142 140 138 136 134 132 130 128 126 124 155 153 151 149 147 145 143 141 139 137 135 133 131 129 127 125 123 163 161 159 180 178 176 174 172 170 168 166
Output Enable
enscan4 enscan4 enscan4 enscan4 enscan4 enscan4 enscan4 enscan4 enscan4
enscan4 enscan4 enscan6 enscan3
enscan3 enscan3 enscan3 enscan3
enscan5
EMDATA30
EMDATA29
bidir
bidir
bidir
bidir
122
120
121
119
enscan5
enscan5
MC92501 44
MOTOROLA
Table 6. Boundary Scan Bit Denition Signal Name
EMDATA28 EMDATA27 EMDATA26 EMDATA25 EMDATA24 EMDATA23 EMDATA22 EMDATA21 EMDATA20 EMDATA19 EACEN EMWR EMDATA18 EMDATA17 EMDATA16 EMDATA15 EMDATA14 EMDATA13 EMDATA12 EMDATA11 EMDATA10 EMDATA9 EMDATA8 EMDATA7 EMDATA6 EMDATA5 EMDATA4 EMDATA3 EMDATA2 EMDATA1 EMDATA0 EMADD23 EMADD22 EMADD21
I/O Cell Type
bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir three-state three-state bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir
System Mode
bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir out out bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir out out out
Scan Bit #
118 116 114 112 110 108 106 104 102 100 98 97 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 95 93 91 89 87 85 83 81 79 77 75 73 71 69 67 65 63 61 59 57 55 53 117 115 113 111 109 107 105 103 101 99
Output Enable
enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5
enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5 enscan5
MOTOROLA
MC92501 45
Table 6. Boundary Scan Bit Denition Signal Name
EMADD20 EMADD19 EMADD18 EMADD17 EMADD16 EMADD15 EMADD14 EMADD13 EMADD12 EMADD11 EMADD10 EMADD9 EMADD8 EMADD7 EMADD6 EMADD5 EMADD4 EMADD3 EMADD2 EMBSH0 EMBSH1 EMBSH2 EMBSH3 EMBSL0 EMBSL1 EMBSL2 EMBSL3 ARST enscan1 enscan2 enscan3 enscan4 enscan5 enscan6
I/O Cell Type
bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir bidir three-state three-state three-state three-state three-state three-state three-state three-state in (core macro) (core macro) (core macro) (core macro) (core macro) (core macro)
System Mode
out out out out out out out out out out out out out out out out out out out out out out out out out out out in
Scan Bit #
52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15
Output Enable
MC92501 46
MOTOROLA
SECTION 16. ELECTRICAL CHARACTERISTICS 16.1. Electrical Specification for Clocks and Interfaces
Electrical specications for the clocks, microprocessor interface timing, PHY interface timing, switch interface timing, and external memory interface timing are identical to the MC92500. Please refer to document MC92500/D for specic values.
16.2.
DC Electrical Characteristics
This device contains protection circuitry to guard against damage due to high static voltages or electric elds. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to 0 (Vin, Vout) 5.5 V. Unused outputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
ABSOLUTE MAXIMUM RATINGS (See Note)
Symbol VDD Vin3 Vout3,4 I I Tstg TL Parameter DC Supply Voltage DC Input Voltage (5 V Tolerant) DC Output Voltage DC Current Drain per Pin, Any Single Input or Output DC Current Drain VDD and VSS Pins Storage Temperature Lead Temperature (10-Second Soldering) Value/Value Range - 0.5 to 3.8 - 0.5 to 5.8 - 0.5 to VDD +0.5 50 100 - 65 to 150 300 Unit V V V mA mA C C
NOTE: Maximum ratings are those values beyond which damage to the device may occur.
RECOMMENDED OPERATING CONDITIONS (To Guarantee Functionality)
Parameter DC Supply Voltage, VDD = 3.3 V (Nominal) Input Voltage (5 V Tolerant) Commercial Operating Temperature Symbol VDD Vin4 TA Min 3.0 0 0 Max 3.6 5.5 70 Unit V V C
NOTES: 1. All parameters are characterized for dc conditions after thermal equilibrium has been established. 2. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). 3. All input, bidirectional, and MDTACK are 5 V tolerant. 4. SRXDATAx, SRXSOC, SRXPRTY, TDO three-state outputs must be constrained to 0 Vout < VDD in High-Z state.
PRELIMINARY DC ELECTRICAL CHARACTERISTICS (TA = 0 to 70C) VDD = 3.3 V 0.3 V
Symbol VIH VIL Iin Parameter TTL Inputs (5 V Tolerant) TTL Inputs (5 V Tolerant) Input Leakage Current, No Pull Resistor With Pullup Resistor* With Pulldown Resistor* IOH Output High Current, LVTTL Output Type Outputs: EACEN, EMWR, EMADDx, EMBSHx, EMBSLx Output High Current, LVTTL Output Type Outputs: All Other Outputs IOL Output Low Current, LVTTL Output Type Outputs: EACEN, EMWR, EMADDx, EMBSHx, EMBSLx Output Low Current, LVTTL Output Type Outputs: All Other Outputs IOZ IDDQ IDD Output Leakage Current, Three-State Output Max Quiescent Supply Current Max Dynamic Supply Current Output = High Impedence, Vout = VDD or VSS Iout = 0 mA Vin = VDD or VSS Nominal Load Capacitance, ACLK = 25.6 MHz, MCLK = 33 MHz VDD = Min, VOL Max = 0.4 V VDD = Min, VOH Min = 0.8 VDD Vin = VDD or VSS Condition Min 2.2 - 0.3 -5 - 50 5 - 24 -4 24 4 - 10 TBD TBD Max 5.5 0.8 5 -5 50 N N N N 10 TBD TBD mA mA mA mA mA Unit V V mA
Ci
Input Capacitance (TTL)
8
pF
*Inputs may be modied to include pull resistors at any time.
MOTOROLA
MC92501 47
SECTION 17. PACKAGING INFORMATION 17.1. Additional Pins
The following pins have been added: D14 N MP Data Acknowledge0 (MDTACK1), and C15 N Receive Address 4 (RXADDR4). These pins do not appear on the MC92500.
17.2.
Package Pin
C3 A2 B2 D5 A3 B4 C5 A4 B5 C6 D7 A5 B6 C7 A6 B7 A7 C8 B8 V15 U14 Y16 W15 Y15 W14 Y14 V13 W13 Y13 U12 V12 W12 Y12 U11 V11 W11 Y11 Y10 V10
Pin Assignment
Signal Name
TESTOUT ACLK TESTSEL MADD:17 MADD:16 MADD:15 MADD:14 MADD:13 MADD:12 MADD:11 MADD:10 MADD:9 MADD:8 MADD:7 MADD:6 MADD:5 MADD:4 MADD:3 MADD:2 EMADD:4 EMADD:3 EMADD:2 N/C EMBSH:0 EMBSH:1 EMBSH:2 EMBSH:3 N/C EMBSL:0 EMBSL:1 EMBSL:2 EMBSL:3 N/C AMODE:1 AMODE:0 ARST TCK TRST TMS
Package Pin
A8 D9 C9 B9 A9 D10 C10 B10 A10 A11 C11 B11 A12 B12 C12 D12 A13 B13 C13 W10 Y9 W9 V9 U9 Y8 W8 V8 Y7 W7 V7 Y6 W6 U7 V6 Y5 W5 V5 Y4 Y3
Signal Name
MSEL MREQ:0 MREQ:1 MDTACK0 MINT MREQ:2 MCLK MWR MWSH/A1 MWSL/SIZE MDS SRXENB SRXDATA:7 SRXDATA:6 SRXDATA:5 SRXDATA:4 SRXDATA:3 SRXDATA:2 SRXDATA:1 TDO TDI ENID STXCLK STXCLAV STXSOC STXPRTY STXDATA:7 STXDATA:6 STXDATA:5 STXDATA:4 STXDATA:3 STXDATA:2 STXDATA:1 STXDATA:0 STXENB TXENB TXFULL TXCCLR TXPHYIDV/ TXADDR4
Package Pin
A14 B14 C14 A15 B15 D14 C15 A16 B16 C16 A17 A18 D16 C17 B17 C18 B20 C19 D18 U5 V4 W4 V3 W1 V2 U3 T4 V1 U2 T3 U1 T2 R3 P4 T1 R2 P3 R1 P2
Signal Name
SRXDATA:0 SRXCLK SRXCLAV SRXSOC SRXPRTY MDTACK1 RXADDR4 RXSOC RXENB RXEMPTY RXPHYID:3 RXPHYID:2 RXPHYID:1 RXPHYID:0 RXPRTY RXDATA:7 RXDATA:6 RXDATA:5 RXDATA:4 TXPRTY TXSOC TXDATA:7 TXDATA:6 TXDATA:5 TXDATA:4 TXDATA:3 TXDATA:2 TXDATA:1 TXDATA:0 TXPHYID:3 TXPHYID:2 TXPHYID:1 TXPHYID:0 MDATA:31 MDATA:30 MDATA:29 MDATA:28 MDATA:27 MDATA:26
Package Pin
E17 C20 D19 E18 D20 E19 F18 G17 E20 F19 G18 F20 G19 G20 H18 H19 H20 J17 J18 P1 N3 N2 N1 M4 M3 M2 M1 L4 L3 L2 L1 K1 K3 K2 J1 J2 J3 J4 H1
Signal Name
RXDATA:3 RXDATA:2 RXDATA:1 RXDATA:0 EMDATA:31 EMDATA:30 EMDATA:29 EMDATA:28 EMDATA:27 EMDATA:26 EMDATA:25 EMDATA:24 EMDATA:23 EMDATA:22 EMDATA:21 EMDATA:20 EMDATA:19 EACEN EMWR MDATA:25 MDATA:24 MDATA:23 MDATA:22 MDATA:21 MDATA:20 MDATA:19 MDATA:18 MDATA:17 MDATA:16 MDATA:15 MDATA:14 MDATA:13 MDATA:12 MDATA:11 MDATA:10 MDATA:9 MDATA:8 MDATA:7 MDATA:6
Package Pin
J19 J20 K17 K18 K19 K20 L20 L18 L19 M20 M19 M18 M17 N20 N19 N18 P20 P19 R20 H2 H3 G1 G2 G3 F1 F2 G4 F3 E1 E2 E3 D1 C1 D2
Signal Name
EMDATA:18 EMDATA:17 EMDATA:16 EMDATA:15 EMDATA:14 EMDATA:13 EMDATA:12 EMDATA:11 EMDATA:10 EMDATA:9 EMDATA:8 EMDATA:7 EMDATA:6 EMDATA:5 EMDATA:4 EMDATA:3 EMDATA:2 EMDATA:1 EMDATA:0 MDATA:5 MDATA:4 MDATA:3 MDATA:2 MDATA:1 MDATA:0 MADD:25 MADD:24 MADD:23 MADD:22 MADD:21 MADD:20 MADD:19 MADD:18 VCOCTL
Package Pin
R19 P17 R18 T20 T19 U20 V20 T17 U18 U19 V18 Y19 W18 V17 U16 Y18 W17 Y17 W16
Signal Name
EMADD:23 EMADD:22 EMADD:21 EMADD:20 EMADD:19 EMADD:18 EMADD:17 EMADD:16 EMADD:15 EMADD:14 EMADD:13 EMADD:12 EMADD:11 EMADD:10 EMADD:9 EMADD:8 EMADD:7 EMADD:6 EMADD:5
MC92501 48
MOTOROLA
17.3.
256-Lead GTBGA Outline PACKAGE DIMENSIONS
GLOB-TOP BALL GRID ARRAY (GTBGA) PACKAGE GC SUFFIX CASE 1208-01
X Y
D F
DETAIL K
4X
R2
M
4X
R1 5
0.35 Z
E
G
A
A3
A1
0.20
A2 Z 4
0.15 Z
ROTATED 90 _ CLOCKWISE
12.78 SQUARE ZONE T
DETAIL K
M
19X
e
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994.
3
256X
0.30 0.10
b
Z Z X Y
S
A B C D E F G H J K L M N P R T U V W Y 20 15 5 1
2.
3.
DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z.
4.
DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.
19X
e
5.
PARALLELISM REQUIREMENT APPLIES TO ZONE T ONLY. PARALLELISM REQUIREMENT SHALL EXCLUDE ANY EFFECT OF LASER MARK ON TOP SURFACE OF PACKAGE.
S
VIEW MM
DIM A A1 A2 A3 b D E e F G R1 R2 R1
MILLIMETERS MIN MAX
--0.50 2.83 0.70
0.56 REF 1.15 0.65 1.49 0.85
27.00 BSC 27.00 BSC 1.27 BSC 17.78 17.78 24.00 24.00
2.50 REF 0.40 2.50
0.635 BSC
MOTOROLA
MC92501 49
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MC92501 50
MOTOROLA
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MOTOROLA
MC92501 51
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specically disclaims any and all liability, including without limitation consequential or incidental damages. OTypicalO parameters can and do vary in different applications and actual performance may vary over time. All operating parameters, including OTypicalsO, must be validated for each customer application by customerOs technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its ofcers, employees, subsidiaries, afliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Afrmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405; Denver, Colorado 80217. 303-675-2140 or 1-800-441-2447 Mfax: RMFAX0@email.sps.mot.com TOUCHTONE (602) 244-6609 US & Canada ONLY 1-800-774-1848 INTERNET: http://motorola.com/sps JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Ofce, 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. 81-3-5487-8488 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
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